Semicoductor device having defect type compound layer between single crystal substrate and single crystal growth layer

• US 5,508,554 A
• Filed: 08/23/1994
• Issued: 04/16/1996
• Est. Priority Date: 08/26/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kikawa, Takeshi, Takatani, Shinichiro, Uchida, Yoko
• Primary Examiner(s): Fahmy, Wael M.
• Application Number:
  US08/294,504
• Time in Patent Office: 602 Days
• Field of Search: 257/617, 257/590, 257/192, 257/194, 257/197, 257/198, 257/611, 257/612
• US Class Current: 257/617
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body

Abstract

Disclosed is a semiconductor device capable of suppressing the generation of dislocations due to the difference in lattice constant by insertion of one or more defect type compound layers in a semiconductor layered structure. The strain generated by the mismatch of the lattice is relaxed by a large amount of vacancies contained in the defect type compound layer, to suppress the generation and the propagation of dislocations, thus inexpensively fabricating a semiconductor device with less deterioration of the characteristics due to defects with good repeatability.

Claims

1. A semiconductor device having at least one semiconductor layered structure, each semiconductor layered structure comprising:

a single crystal substrate;

a semiconductor single crystal growth layer which is formed on said single crystal substrate; and

a defect type compound layer inserted between said single crystal substrate and said single crystal growth layer so as to be contacted therewith, the defect type compound layer being made of at least one defect type compound having a crystal structure in which part of lattice sites of the crystal structure is vacant;

wherein materials of said single crystal substrate and said single crystal growth layer and a thickness of said single crystal growth layer are determined such that, when another single crystal substrate made of a same material as that of said single crystal substrate is prepared, and a layer made of a same material as that of said single crystal growth layer is directly grown on the another single crystal substrate to a same thickness as that of said single crystal growth layer without any defect type compound layer, dislocations are generated in the layer made of the same material as that of said single crystal growth layer; and

a thickness of said defect type compound layer is determined such that, when another single crystal substrate made of the same material as said single-crystal substrate is prepared, and a layer made of a same material as that of said defect type compound layer is directly grown on the another single crystal substrate to a same thickness as that of said defect type compound layer without any single crystal growth layer, any dislocation is not generated in the layer made of the same material as that of said defect type compound layer.

2. A semiconductor device according to claim 1, wherein the material of said single crystal substrate is a semiconductor.

3. A semiconductor device according to claim 1, wherein said defect type compound layer includes a plurality of sub-layers of the at least one defect type compound, the device having a structure that layers made of a same material as that of said single crystal growth layer and the sub-layers are alternately stacked, the alternately stacked layers and sub-layers being positioned between the substrate and growth layer, and both an uppermost layer and a lowermost layer of the alternately stacked layers and sub-layers are composed of the sub-layers of said at least one defect type compound;

and

a thickness of each of the plurality of sub-layers made of the at least one defect type compound is such that, when a layer of said at least one defect type compound is formed on said single crystal substrate or the layer made of the same material as that of said single crystal growth layer, no dislocation is generated in the layer made of the at least one defect type compound.

4. A semiconductor device according to claim 2, wherein the material of said single crystal substrate is selected from a group consisting of Si, GaAs and InP.

5. A semiconductor device according to claim 4, wherein the material of said single crystal growth layer is selected from a group consisting of GaAs, AlGaAs, InGaAs, and InAlAs.

6. A semiconductor device according to claim 5, wherein said defect type compound layer is one selected from the group consisting of a Ga₂ Se₃ layer and a Ga₂ S₃ layer.

7. A semiconductor device according to claim 1, wherein an ohmic electrode is formed on said single crystal growth layer so as to be contacted therewith;

and

wherein said single crystal growth layer is of a conductivity type selected from the group consisting of n-type conductivity and p-type conductivity,

when said single crystal growth layer is of the n-type conductivity, an electron energy at a minimum of a conduction band of said single crystal growth layer is smaller than that of said single crystal substrate, and

when said single crystal growth layer is of the p-type conductivity, an electron energy at a maximum of a valence band of said single crystal growth layer is larger than that of said single crystal substrate.

8. A semiconductor device according to claim 7, wherein said single crystal substrate includes a conducting channel layer of a field effect transistor,

said single crystal growth layer includes two single crystal growth layer portions, which respectively are disposed on side surfaces of said conducting channel layer by way of said defect type compound layer, and

said ohmic electrode includes two ohmic electrode portions which respectively constitute a source electrode and a drain electrode.

9. A semiconductor device according to claim 7, wherein said single crystal substrate includes a base layer of a bipolar transistor, the base layer having side surfaces,

said single crystal growth layer is disposed on the side surfaces of said base layer by way of said defect type compound layer, and

said ohmic electrode constitutes a base electrode.

10. A semiconductor device according to claim 9, wherein said single crystal substrate includes a GaAs wafer, and an undoped GaAs layer, an n-type GaAs collector layer, a p-type GaAs base layer, and an n-type AlGaAs emitter layer which are sequentially formed on the GaAs wafer, said p-type GaAs base layer and said n-type AlGaAs emitter layer each having side surfaces;

and

said single crystal growth layer includes a p-type InGaAs layer, which is disposed on both of the side surfaces of said p-type GaAs base layer and of said n-type AlGaAs emitter layer and on an area of said n-type GaAs collector layer, continuous to said side surfaces of said p-type GaAs base layer, not covered with said p-type GaAs base layer and said n-type AlGaAs emitter layer, by way of said defect type compound layer, said defect type compound layer being composed of Ga₂ Se₃.

11. A semiconductor device according to claim 1, wherein said single crystal growth layer includes a conducting channel layer of a field effect transistor.

12. A semiconductor device according to claim 11, wherein said single crystal substrate includes an Si substrate;

said defect type compound layer is a Ga₂ Se₃ layer;

said single crystal growth layer is an undoped GaAs layer that constitutes said conducting channel layer and is disposed on the Si substrate by way of said defect type compound layer of Ga₂ Se₃ ;

an n-type AlGaAs layer is formed on said undoped GaAs layer;

a source electrode and a drain electrode are disposed on paid n-type AlGaAs layer by way of a GaAs cap layer; and

a gate electrode is formed on said n-type AlGaAs layer in a recess portion constituted of said GaAs cap layer.

13. A semiconductor device according to claim 8, wherein said conducting channel layer is an n-type InGaAs layer, said single crystal growth layer is an n-type InGaAs layer, and said defect type compound layer is a Ga₂ Se₃ layer.

14. A semiconductor device according to claim 1, which includes two semiconductor layered structures, said single crystal growth layer of one of the two semiconductor layered structures including a conducting channel layer of a field effect transistor, and wherein the single crystal growth layer of the other of the two semiconductor layered structures has two single crystal growth layer portions respectively serving as a source and a drain of said field effect transistor, the single crystal growth layer of said one of the two semiconductor layered structures being said single crystal substrate of the other of the two semiconductor layered structures.

15. A semiconductor device according to claim 14, wherein said single crystal growth layer of said one of the two semiconductor layered structures includes an undoped InGaAs conducting channel layer, which is disposed on said single crystal substrate composed of a GaAs substrate and an undoped GaAs layer formed on said GaAs substrate, by way of said defect type compound layer composed of a Ga₂ Se₃ layer,

said single crystal growth layer of the other of the two semiconductor layered structures constitutes an n-type AlGaAs carrier supply layer, which is disposed on said conducting channel layer by way of said defect type compound layer composed of a Ga₂ Se₃ layer,

a source electrode and a drain electrode are disposed on said n-type AlGaAs carrier supply layer by way of a GaAs cap layer, and

a gate electrode is formed on said n-type AlGaAs carrier supply layer in the recess portion composed of said GaAs cap layer.

16. A semiconductor device according to claim 1, wherein said single crystal growth layer includes a buffer layer to the substrate of a bipolar transistor, and an active portion of said bipolar transistor is formed on said buffer layer.

17. A semiconductor device according to claim 16, wherein said single crystal substrate includes an Si substrate, and said single crystal growth layer includes an undoped GaAs layer and is disposed on said single crystal substrate by way of said defect type compound layer composed of a Ga₂ Se₃ layer.

18. A semiconductor device according to claim 1, which includes two semiconductor layered structures, wherein said single crystal growth layer of one of the two semiconductor layered structures includes a base layer of a heterojunction bipolar transistor, and said single crystal growth layer of the other of the two semiconductor layered structures includes an emitter layer of said heterojunction bipolar transistor, and said single crystal growth layer of the one of the two semiconductor layered structures also is the single crystal substrate of the other of the two semiconductor layered structures.

19. A semiconductor device according to claim 18, wherein said base layer contained in said single crystal growth layer of said one of the two semiconductor layered structures is made of a p-type In_x Ga_1-x As (x=0.8 to 1.0), and which is formed on said single crystal substrate composed of an InP substrate, an undoped InP layer and n-type In_y Ga_1-y As collector (y=0.53) being sequentially formed on said InP substrate, by way of said defect type compound layer composed of a Ga₂ Se₃ layer, and

said emitter layer contained in said single crystal growth layer of the other of the two semiconductor layered structures is made of an n-type In_z Al_1-z As (z=0.53) and which is formed on said base layer by way of said defect type compound layer composed of a Ga₂ Se₃ layer.

20. A semiconductor device according to claim 1, wherein the at least one defect type compound has a stoichiometric composition but has part of the lattice sites of the crystal structure thereof vacant.

21. A semiconductor device according to claim 1, wherein the at least one defect type compound is a chalcogenite of a Group III element.

22. A semiconductor device according to claim 1, wherein the at least one defect type compound includes a compound selected from the group consisting of Ag₂ HgI₄ and HgGa₂ Te₄.

23. A semiconductor device according to claim 1, wherein the at least one defect type compound includes a mixture of defect type compounds.

24. A semiconductor device according to claim 1, wherein the defect type compound layer is a layer formed by reacting material of the single crystal substrate with at least one other element so as to form the at least one defect type compound.

25. A semiconductor device according to claim 1, wherein the defect type compound layer is provided in an active region of the semiconductor device.