Special interconnect layer employing offset trace layout for advanced multi-chip module packages

• US 5,508,938 A
• Filed: 09/21/1993
• Issued: 04/16/1996
• Est. Priority Date: 08/13/1992
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Wheeler, Richard L.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US08/125,035
• Time in Patent Office: 938 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 257/684, 257/685, 257/700, 257/758, 29/846, 29/847, 437/180, 437/189, 437/195, 307/409
• US Class Current: 716/112
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A multi-layer printed wiring board design method employs establishing of critical and non-critical signal layers with first and second design rule sets assigned respectively. A configuration employing y x y'"'"' layers wherein conductors in the y and y'"'"' layers are orthogonal to x layers and y'"'"' layers are offset by approximately one-half pitch from y layers for cross talk reduction.

Claims

1. A method for multi-layer printed wiring board design comprising the steps of:

establishing a first category of critical signals;

defining design rules for first conductor spacing and first conductor characteristics to reduce degradation of the critical signals;

identifying a favored direction for bus interconnection;

defining a first orientation of adjacent signal planes to employ the first design rules having at least one "y" plane oriented at 0°

relative to the favored direction, at least one "x" plane separated from said y plane by a dielectric layer having conductors oriented at 90°

to the favored direction and at least one "y'"'"'" plane separated from said x plane by a dielectric layer having conductors oriented at 0°

with respect to the favored direction, said conductors of the "y'"'"'" plane offset from the conductors of the "y" plane by approximately one-half pitch;

laying out at least one plurality of first signal planes using the first design rules and first orientation;

establishing a second category of non-critical signals,

defining second design rules for second conductor spacing and second conductor characteristics for said non-critical signals; and

laying out at least one plurality of second signal planes employing the second design rules.

2. A method as defined in claim 1 further comprising the steps of:

identifying a second favored direction for bus interconnection;

defining a second orientation of adjacent signal planes to employ the second design rules having at least one second "y" plane oriented at 0°

relative to the favored direction, at least one second "x" plane having conductors oriented at 90°

to the favored direction and at least one second "y'"'"'" plane having conductors oriented at 0°

with respect to the favored direction, said conductors of the second "y'"'"'" plane offset from the conductors of the second "y" plane by approximately one-half pitch; and

wherein said step of laying out at least one plurality of second signal planes employs said second orientation.

3. A method as defined in claim 1 wherein the step of establishing the first category of critical signals includes:

selecting clock signals;

selecting control signals; and

selecting asynchronous signals.

4. A method as defined in claim 3 wherein the step of establishing critical signals further includes selecting signals requiring vias of greater than one layer.

5. A method as defined in claim 3 wherein the step of selecting critical signals further includes selecting signals having a path extending beyond two chips in length.

6. A method as defined in claim 1 wherein the step of defining second design rules further comprises determining second conductor spacing and second conductor characteristics to establish a conductor density of at least a factor of four greater than the density established by the first conductor spacing and first conductor characteristics.

7. A method as defined in claim 3 wherein the step of establishing critical signals includes selecting signals potentially requiring engineering changes.

8. A method as defined in claim 3 wherein the step of establishing critical signals includes selecting signals requiring off-chip termination.