Capacitor, electrode structure, and semiconductor memory device

• US 5,508,953 A
• Filed: 05/16/1994
• Issued: 04/16/1996
• Est. Priority Date: 05/14/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Numata, Ken, Fukuda, Yukio, Aoki, Katsuhiro, Nishimura, Akitoshi
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/242,924
• Time in Patent Office: 701 Days
• Field of Search: 365/145, 365/149, 365/117, 257/295, 257/296, 257/298, 257/300
• US Class Current: 365/145
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

Claims

1. A capacitor comprising:

an electrically interconnecting layer;

a barrier metal layer deposited on the interconnecting layer to prevent oxidation of the interconnecting layer;

an oxidation-resistant lower electrode disposed above the barrier metal layer;

a dielectric film of high dielectric constant, comprising primary and secondary components, deposited on the lower electrode;

an upper electrode deposited on the dielectric film; and

a diffusion barrier layer interposed between the barrier metal layer and the lower electrode, comprising a material preventing the primary component of the dielectric film from diffusing into the electrically interconnecting layer.

2. The capacitor of claim 1 wherein the dielectric film comprises a ferroelectric material having Pb as the primary component, and the diffusion barrier layer comprises tungsten for preventing Pb from diffusing from the dielectric film to the electrically interconnecting layer.

3. The capacitor of claim 1 wherein the electrically interconnecting layer comprises polysilicon, the dielectric film comprises a ferroelectric material having Pb as the primary component, and the diffusion barrier layer comprises tungsten for preventing Pb from diffusing from the dielectric film to the electrically interconnecting layer.

4. The capacitor of claim 1 wherein the electrically interconnecting layer comprises an n⁺ -type silicon, the dielectric film comprises a ferroelectric material having Pb as the primary component, and the diffusion barrier layer comprises tungsten for preventing Pb from diffusing from the dielectric film to the electrically interconnecting layer.

5. The capacitor of claim 1 wherein the interconnecting layer is formed on an insulating substrate.

6. The capacitor of claim 1 wherein the barrier metal layer is formed to surround the diffusion barrier layer.

7. A semiconductor memory cell comprising:

a transistor memory circuit; and

a capacitor coupled to the transistor circuit, the capacitor comprising;

an electrically interconnecting layer,

a barrier metal layer deposited on the interconnecting layer to prevent oxidation of the interconnecting layer,

an oxidation-resistant lower electrode disposed above the barrier metal layer,

a dielectric film of high dielectric constant, comprising primary and secondary components, deposited on the lower electrode,

an upper electrode deposited on the dielectric film, and

a diffusion barrier layer interposed between the barrier metal layer and the lower electrode, comprising a material preventing the primary component of the dielectric film from diffusing into the electrically interconnecting layer.