Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through

• US 5,508,957 A
• Filed: 09/26/1994
• Issued: 04/16/1996
• Est. Priority Date: 09/18/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Masuoka, Fujio, Kirisawa, Ryouhei, Inoue, Satoshi, Shirota, Riichiro, Iwata, Yoshihisa, Momodomi, Masaki, Iwahashi, Hiroshi, Chiba, Masahiko, Watanabe, Shigeyoshi, Itoh, Yasuo, Ohuchi, Kazunori, Nakayama, Ryozo
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/312,072
• Time in Patent Office: 568 Days
• Field of Search: 395/425, 395/430, 365/104, 365/184, 365/185, 365/189.05, 365/238.5, 257/315, 257/316
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

Claims

1. An electrically programmable semiconductor memory device comprising:

a semiconductive substrate;

a plurality of data storage transistors formed in a surface area of said substrate and including a plurality of transistors coupled to each other in series each having an insulated carrier storage layer and a control gate disposed over and insulated from said carrier storage layer;

a plurality of bit lines one of which is coupled to said plurality of transistors;

first switch means connected to said plurality of transistors at a first node thereof, for selectively coupling said plurality of transistors to the one bit line;

second switch means connected to said plurality of transistors at a second node thereof for selectively coupling said plurality of transistors to a source potential;

program means for, while sequentially programming said plurality of transistors, changing an amount of charge carriers stored in the carrier storage layer of a selected transistor of said plurality of transistors by tunneling to cause said selected transistor to be programmed with given data, said program means causing said first switch means and said second switch means to turn on applying a first voltage to the one bit line, applying a second voltage to the control gate of the selected transistor, and applying a voltage to the control gate of each non-selected transistor to render each non-selected transistor conductive so that the first voltage is transmitted from the one bit line to said selected transistor; and

wherein said first switch means includes a first insulated gate transistor and said second switch means includes a second insulated gate transistor, said first insulated gate transistor has a greater channel length than that of said second insulated gate transistor.

2. The memory device according to claim 1, wherein said data storage transistors comprise floating gate metal oxide semiconductor field effect transistors.

3. The memory device according to claim 1, wherein the program means erases said plurality of transistors by causing the first and second switch means to turn off, and applying the third voltage to the control gate of each of said plurality of transistors.

4. An electrically programmable and erasable semiconductor memory device comprising:

a semiconductor substrate;

an array of memory cell transistors formed in a surface area of said substrate, said transistors including a plurality of memory cell transistors coupled in series between first and second nodes, each memory cell transistor having a control gate and an insulated charged storage layer;

a plurality of bit lines including a bit line connected with said plurality of memory cell transistors at the first node through a first switching transistor;

word lines connected to control gates of said plurality of memory cell transistors;

a second switching transistor coupled between the second node and a source potential;

program means for allowing said plurality of memory cells to be written with data bits sequentially while causing said first and second switching transistors to turn on, and for, when a selected memory cell transistor is to be programmed, applying a high level voltage to at least one first non-selected memory cell transistor positioned between said first switching transistor and said selected memory cell transistor so as to permit a data bit to be transmitted from a bit line toward said selected memory cell transistor by way of said first switching transistor and said at least one first non-selected memory cell transistor, while applying a low level voltage to at least one second non-selected memory cell transistor, whereby tunneling of charge carriers occurs in the charge storage layer of said selected memory cell transistor; and

wherein

said first switching transistor has a channel length greater than that of said second switching transistor and those of said memory cell transistors so that an occurrence of punch through decreases in said first switching transistor.

5. The device according to claim 4, wherein each of said first and second switching transistors includes an insulated gate metal oxide semiconductor field effect transistor.

6. The device according to claim 5, wherein each of said plurality of memory cell transistors includes a floating-gate metal oxide semiconductor field effect transistor.