Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage

• US 5,508,958 A
• Filed: 09/29/1994
• Issued: 04/16/1996
• Est. Priority Date: 09/29/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Fazio, Albert, Bauer, Mark E., Atwood, Gregory E.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/315,292
• Time in Patent Office: 565 Days
• Field of Search: 365/184, 365/210, 365/168, 365/218, 365/185.33, 365/185.19
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A method and apparatus for sensing the state of floating gate memory cells in a memory array. Because of its stability and accuracy, the sensing apparatus may be used for sensing the state of multi-bit floating gate memory cells. The state of a memory cell is sensed by applying a variable gate voltage to the top gate of the floating gate memory cell and comparing the cell current to a fixed reference current. A circuit detects when the cell current is equal to the reference current. When the currents are equal, the value of the variable gate voltage indicates the state of the memory cell. For one embodiment, an analog-to-digital converter converts the variable gate voltage to a digital value that is latched when the currents are equal. The latched digital value indicates the state of the memory cell. For this embodiment, a ramp voltage or other suitable variable voltage may be used as the variable gate voltage. For another embodiment, a digital-to-analog converter is used to generate the variable gate voltage. A counter generates digital values to step the variable gate voltage. When the cell current equals the fixed reference current, the digital counter value is latched to indicate the state of the memory cell.

Claims

1. An apparatus for determining a state of a memory cell that is programmed to one of a plurality of states, comprising:

a voltage circuit that applies a variable voltage to a gate of the memory cell during a data reading operation, wherein the memory cell generates a cell current that is proportional to the variable voltage;

a reference current circuit that provides a fixed reference current;

a current comparing circuit coupled to the memory cell and the reference current circuit, the current comparing circuit detecting when the cell current is substantially equal to the fixed reference current, wherein the cell current is substantially equal to the fixed reference current when the variable voltage assumes a first voltage value that reflects the state of the memory cell; and

a state sensing circuit coupled to the current comparing circuit, the state sensing circuit determining the state of the memory cell according to the first voltage value of the variable voltage at which the cell current is substantially equal to the fixed reference current.

2. The apparatus of claim 1, further comprising:

a converting circuit that converts the first voltage value of the variable voltage to a digital value, wherein the digital value represents the state of the memory cell when the cell current is substantially equal to the fixed reference current.

3. The apparatus of claim 2, wherein the state sensing circuit further comprises a latch that latches the digital value from the converting circuit when the current comparing circuit detects that the cell current is substantially equal to the fixed reference current.

4. The apparatus of claim 1, further comprising:

a digital-to-analog converter, coupled to the gate of the memory cell, for generating the variable voltage; and

a counter, coupled to the digital-to-analog converter, for providing one of a plurality of digital values to the digital-to-analog converter, wherein the digital-to-analog converter generates the variable voltage in response to the provided digital value.

5. The apparatus of claim 4 further comprising a latch, responsive to the current comparing circuit, for latching the digital value provided to the digital-to-analog converter when the cell current is substantially equal to the fixed reference current, wherein the latched digital value represents the state of the memory cell.

6. The apparatus of claim 5 wherein the counter provides sequential digital values such that the variable voltage is a stepped voltage.

7. The apparatus of claim 1 further comprising an analog-to-digital converter, coupled to receive the variable voltage, for converting the variable voltage to a digital value.

8. The apparatus of claim 7 further comprising a latch circuit, responsive to the current comparing circuit, for latching the digital value when the cell current is substantially equal to the fixed reference current, wherein the latched digital value represents the state of the memory cell.

9. The apparatus of claim 8 wherein the analog-to-digital converter comprises a plurality of programmable reference cells, the variable voltage being applied to the programmable reference cells.

10. The apparatus of claim 9 wherein the variable voltage is a ramp voltage.

11. The apparatus of claim 1, wherein the fixed reference current is chosen such that the cell current is substantially independent of temperature when the state sensing of the memory cell occurs, wherein the state sensing is substantially independent of temperature.

12. The apparatus of claim 11 wherein the fixed reference current is between about 10-20 μ

A.

13. The apparatus of claim 11 wherein the fixed reference current is chosen such that variation in transconductance of the memory cells is also minimized.

14. An apparatus, comprising:

a memory cell having a floating gate, wherein the memory cell is programmed to one of a plurality of states corresponding to an amount of charge stored on the floating gate, the memory cell having a top gate, a source, and a drain;

a bias circuit coupled between the drain and source of the memory cell, for establishing a fixed voltage across the source and drain of the memory cell;

a variable voltage circuit coupled to the top gate of the memory cell, the variable voltage circuit applies a variable voltage to the top gate of the memory cell during a data reading operation, wherein the memory cell generates a cell current proportional to the variable voltage;

a reference current circuit that provides a substantially constant reference current;

a sensing circuit coupled to the reference current circuit and the memory cell, the sensing circuit indicating when the cell current is substantially equal to the reference current, wherein the cell current is substantially equal to the reference current when the variable voltage assumes a voltage value that reflects the state of the memory cell;

a first circuit coupled to the variable voltage circuit, the first circuit generating a digital value corresponding to the voltage value of the variable voltage; and

a latch coupled to the first circuit and responsive to the sensing circuit, the latch latching the digital value when the cell current is substantially equal to the reference current, wherein the latched digital value represents the state of the memory cell.

15. The apparatus of claim 14 wherein the variable voltage circuit is a digital-to-analog converter and the first circuit is a counter.

16. The apparatus of claim 14 wherein the variable voltage is a ramp voltage and the first circuit is an analog-to-digital converter.

17. The apparatus of claim 14 wherein the reference current is chosen such that the cell current is substantially independent of temperature when the cell current is substantially equal to the fixed current.

18. The apparatus of claim 17 wherein the reference current is between about 10-20 μ

A.

19. The apparatus of claim 18 wherein the reference current is chosen such that variation in transconductance of the memory cells is also minimized.

20. An apparatus for determining a state of a memory cell that is programmed to one of a plurality of states, comprising:

means for applying a variable voltage to a gate of the memory cell during a data reading operation, wherein the memory cell generates a cell current that is proportional to the variable voltage;

means for providing a fixed reference current;

means for detecting when the cell current is substantially equal to the fixed reference current, wherein the cell current is substantially equal to the fixed reference current when the variable voltage assumes a first voltage value that reflects the state of the memory cell; and

means for determining the state of the memory cell according to the first voltage value of the variable voltage at which the cell current is substantially equal to the fixed reference current.

21. The apparatus of claim 20, further comprising:

means for converting the first voltage value of the variable voltage to a digital value, wherein the digital value represents the state of the memory cell when the cell current is substantially equal to the fixed reference current.

22. The apparatus of claim 21 further comprising:

means, responsive to the equal current detecting means, for latching the digital value when the cell current is substantially equal to the fixed reference current.

23. A method for sensing a state of a memory cell that is programmed to one of a plurality of states, comprising the steps of:

applying a variable voltage to a gate of the memory cell during a data reading operation, wherein the memory cell generates a cell current that is proportional to the variable voltage;

providing a fixed reference current;

detecting when the cell current is substantially equal to the fixed reference current, wherein the cell current is substantially equal to the fixed reference current when the variable voltage assumes a first voltage value that reflects the state of the memory cell; and

determrining the state of the memory cell according to the first voltage value of the variable voltage at which the cell curent is substantially equal to the fixed reference current. determining the state of the memory cell according to a value of the variable gate voltage when the cell current is substantially equal to the fixed reference current.

24. The method of claim 23, further comprising the step of converting the first voltage value of the variable voltage to a digital value, wherein the digital value represents the state of the memory cell when the cell current is substantially equal to the fixed reference current.

25. The apparatus of claim 24 further comprising the step of latching the digital value when the cell current is substantially equal to the fixed reference current, wherein the latched digital value represents the state of the memory cell.

26. A method for sensing the state of a memory cell, comprising the steps of:

selecting a memory cell to be sensed;

applying a variable gate voltage to a gate of the selected memory cell during a data reading operation, wherein the memory cell generates a cell current proportional to the variable gate voltage;

providing a fixed reference current;

determining whether the cell current is substantially equal to the fixed reference current, wherein the cell current is substantially equal to the fixed reference current when the variable gate voltage assumes a first voltage value that reflects the state of the memory cell;

providing a digital value corresponding to the first voltage value of the variable gate voltage when the cell current is substantially equal to the fixed reference current; and

latching the digital value when the cell current is substantially equal to the fixed reference current, wherein the latched digital value represents the state of the memory cell.