Method and apparatus for execution of operations in a flash memory array

• US 5,509,134 A
• Filed: 06/30/1993
• Issued: 04/16/1996
• Est. Priority Date: 06/30/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Underwood, Keith F., Rozman, Rodney R., Fandrich, Mickey L., Durante, Richard J.
• Primary Examiner(s): Harrell, Robert B.
• Assistant Examiner(s): VU, VIET DUY
• Application Number:
  US08/086,186
• Time in Patent Office: 1,021 Days
• Field of Search: 395/500, 395/183.06, 395/183.10, 395/375, 395/430, 395/500, 395/733, 395/800, 365/230.06, 365/185, 365/189.05, 365/230.01, 365/900
• US Class Current: 711/103
• CPC Class Codes: G06F 9/45512 Command shells
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A flash memory system includes a user interface and array controller. The user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution. The user interface further functions as an arbiter to control the priority of commands to be executed. The array controller performs the operations on the flash array such as program and erase. The array controller consists of a general purpose processor with program memory which is programmable by the user. The program memory stores one or more algorithms that can be executed by the array controller. The algorithm is selected according to the command received at the user interface. The algorithms can be customized simply by programming the program memory. The system further provides an interrupt mechanism which enables the flash memory system to perform a context switch of a higher priority command with the lower priority, but currently executing, command.

Claims

1. A flash memory array system fabricated on a single substrate and coupled to a processing device comprising:

an interrupt status bit, which when set, permits issuance of an interrupt during the execution of a command;

a user interface for receiving commands from the processing device to be executed by the flash memory, said user interface comprising a command queue having storage to store said received commands including a current command executing and logic for issuing an interrupt signal if the interrupt status bit is set and the command queue comprises the current command executing and a next command to be executed;

an array controller coupled to the user interface to receive operations to execute, said array controller controlling power sources to read, erase and program the memory array, said array controller coupled to receive the interrupt signal issued by the user interface;

at least one register coupled to the array controller to store a state of the array controller;

upon receipt of the interrupt signal, said array controller placing the memory array in a predetermined state, saving the state of the array controller, executing an operation corresponding to the next command, restoring the state of the array controller stored in the registers, and continuing execution of an operation corresponding to the current command;

such that interrupts can be processed by the flash memory system without corrupting the flash arrays.

3. The system as set forth in claim 1, wherein said user interface further comprises a command state machine for receiving commands, said command state machine storing one or more commands in the command queue.

4. The system as set forth in claim 1, further comprising at least one algorithm which is executed by the array controller in response to an operation to execute.

5. The system as set forth in claim 4, wherein the algorithm indicates whether the algorithm can be interrupted.

6. The system as set forth in claim 4, wherein the algorithm comprises instructions to be executed, said algorithm including instructions to enable and disable interrupts such that during certain instructions interrupts are prohibited.

7. The system as set forth in claim 6, wherein said instructions comprise an enable interrupt instruction (ENI) which sets the interrupt status bit and identifies an instruction at which the operation corresponding to the current command is to continue execution after execution of the operation corresponding to the next command.

8. The system as set forth in claim 7, wherein said instructions comprises a disable interrupt instruction (DSI) which resets the interrupt status bit.

9. The system as set forth in claim 7, wherein said array controller further comprises an interrupt return register, said interrupt return register storing the identification of the instruction at which the operation corresponding to the current command is to continue execution after execution of the operation corresponding to the next command.

10. The system as set forth in claim 4, wherein the algorithm comprises interrupt start code, said interrupt start code executed when an interrupt is issued.

11. The system as set forth in claim 10, wherein said array controller further comprises an interrupt start register (ISR) and the algorithm comprises instructions to be executed, said instructions comprising a set interrupt start register instruction which when executed sets the interrupt start register to identify the location of the interrupt start code.

12. The system as set forth in claim 10, wherein said interrupt start code comprises instructions which are executed in response to an interrupt, said instructions identifying a point during execution of the operation at which the operation can be safely suspended without corrupting data.

13. The system as set forth in claim 10, wherein said interrupt start code comprises instructions which, when executed, place power sources and read/write circuitry in a state for use during execution of the operation corresponding to the next command.

14. The system as set forth in claim 10, wherein said interrupt start code comprises instructions which, when executed, performs a context switch of the state of the array controller with respect to the operations corresponding to the current command and the next command.

15. The system as set forth in claim 4, wherein the algorithm comprises interrupt return code, said interrupt return code executed at the completion of execution of the operation corresponding to the next command.

16. The system as set forth in claim 15, wherein said interrupt return code causes execution of the operation corresponding to the current command to continue at a safe return point in the operation corresponding to the interrupted current command.

17. The system as set forth in claim 15, wherein said array controller further comprises a program counter which points to an instruction to be executed, said interrupt return code adjusting the program counter to point to an instruction at which to continue execution of the operation corresponding to the current command.

18. The system as set forth in claim 15, wherein said interrupt return code comprises instructions which, when executed, place power sources and read/write circuitry in a state for use during execution of the operation corresponding to the current command.

19. The system as set forth in claim 16, wherein safe return point varies according to the state of execution of the current process when an interrupt is issued.

20. The system as set forth in claim 4, wherein the algorithm determines whether the next command is of a higher priority to interrupt the current command.

21. The system as set forth in claim 1, wherein the current command comprises a command to erase at least a portion of the flash memory array and the next command comprises a command to program at least a portion of the flash memory array, said flash memory system performing a program during erase operation.

22. The system as set forth in claim 1, wherein the user interface comprises a plurality of block status registers indicating a status of the corresponding block, at least one register allocated to each block of the flash memory array, said system executing the current command on a first set comprising at least one block of the flash memory array and executing the next command on a second set comprising at least one block of the flash memory array, said execution of the current command causing the update of corresponding block status registers, said execution of the next command causing the update of the corresponding block status registers, wherein the issuance of the interrupt and the execution of the next command prior to completion of the current command and the corresponding update of the block status registers provides for multiple process execution by a single array controller.

2. A flash memory system fabricated on a single substrate and coupled to a processing device comprising:

a flash array comprising a plurality of flash cells for storage of data;

a user interface for receiving commands from the processing device to be executed by the flash memory system, said user interface comprising a command queue having storage to store said received commands and logic that generates a program memory address identifying the location of code in a program memory which, when executed, performs the command;

an array controller coupled to the user interface to receive the program memory address, said array controller comprising a micro-controller and the program memory, said program memory being programmable by a user to comprise code that is selectively executed by the microcontroller, said program memory address identifying the location of the code in program memory the micro-controller is to execute, said micro-controller performing operations with respect to the flash array in accordance with the code in program memory;

wherein the flash memory system can be programmed to perform a plurality of functions to be performed by the micro-controller, increasing the flexibility of the flash memory system and off loading control of the flash array from the processor device onto the micro-controller.

23. The system as set forth in claim 2, wherein said user interface further comprises a command state machine, said command state machine receiving commands to be executed and initiating the array controller to receive the program memory address and execute code to perform the command.

24. The system as set forth in claim 2, said user interface further comprising a jump table identifying an offset vector for each command to be executed by the array controller into the program memory of the array controller, said offset vector indicating the location of code to be executed in response to the command.

25. The system as set forth in claim 24, wherein the offset vector points to an index location in the program memory, said index location identifying the first address of the code to be executed from the program memory by the array controller.

26. The system as set forth in claim 25, wherein the jump table is configured to map multiple commands to a single offset vector to permit multiple classes of commands, distinguished by the hardware configuration of the flash memory system, to utilize the same code, thereby supporting multiple hardware configurations without modification of the user interface or array controller.

27. The system as set forth in claim 26, wherein the user interface generates at least one hardware configuration signal to the array controller in conjunction with the transmission of the offset vector to identify different hardware configurations.

28. The system as set forth in claim 25, wherein code executed in response to a command can be changed by modifying the starting address stored in the index location to reference a different portion of the program memory.

29. The system as set forth in claim 2, wherein said system further comprising at least one page buffer for receiving and temporarily storing code to be executed by the array controller to perform an update of the program memory, such that if a command is received by the user interface to update the program memory, said user interface causing the array controller to execute the code temporarily stored in the page buffer to update the program memory, wherein the code executed pursuant to a specific command can be modified or code corresponding to additional commands can be added.

30. The system as set forth in claim 2, wherein said commands comprise commands to program and erase the flash array.

31. A system comprising:

a processor for issuing commands;

a bus coupled to the processor;

a flash memory array system fabricated on a single substrate and coupled to the bus comprising;

a flash memory array;

an interrupt status bit, which when set, permits issuance of an interrupt during the execution of a command;

a user interface for receiving commands from the processor to be executed by a flash memory array system, said user interface comprising a command queue having storage to store said received commands including the current command executing and logic for issuing an interrupt signal if the interrupt status bit is set and the command queue comprises the current command executing and a next command to be executed;

an array controller coupled to the user interface to receive operations to execute, said array controller controlling power sources to read, erase and program the flash memory array, said array controller coupled to receive the interrupt signal issued by the user interface;

at least one register coupled to the array controller to store a state of the array controller;

upon receipt of the interrupt signal, said array controller placing the flash memory array in a predetermined state, saving the state of the array controller, executing an operation corresponding to the next command, restoring the state of the array controller stored in the registers, and continuing execution of an operation corresponding to the current command;

such that interrupts can be processed by the flash memory system without corrupting the flash memory arrays.

32. The system as set forth in claim 31, wherein said user interface further comprises a command state machine for receiving commands issued by the processor, said command state machine storing one or more commands in the command queue.

33. The system as set forth in claim 31, further comprising at least one algorithm which is executed by the array controller in response to an operation to execute.

34. The system as set forth in claim 33, wherein the algorithm indicates whether the algorithm can be interrupted to execute the operation corresponding to the next command received from the processor.

35. The system as set forth in claim 34, wherein the algorithm comprises instructions to be executed, said instructions including instructions to enable and disable interrupts such that during execution of certain instructions interrupts are prohibited.

36. The system as set forth in claim 35, wherein said instructions comprise an enable interrupt instruction (ENI) which sets the interrupt status bit and identifies an instruction at which the operation corresponding to the current command is to continue execution after execution of the operation corresponding to the next command.

37. The system as set forth in claim 35, wherein said instructions comprises a disable interrupt instruction (DSI) which resets the interrupt status bit.

38. The system as set forth in claim 35, wherein said array controller further comprises an interrupt return register, said interrupt return register storing the identification of the instruction at which the operation corresponding to the current command is to continue execution after execution of the operation corresponding to the next command.

39. The system as set forth in claim 33, wherein the algorithm comprises interrupt start code, said interrupt start code executed when an interrupt is issued.

40. The system as set forth in claim 39, wherein said array controller further comprises an interrupt start register (ISR) and the algorithm comprises instructions to be executed, said instructions comprising a set interrupt start register instruction which when executed sets the interrupt start register to identify the location of the interrupt start code.

41. The system as set forth in claim 39, wherein said interrupt start code comprises instructions which are executed in response to an interrupt, said instructions identifying a point during execution of the operation corresponding to the command at which the operation corresponding to the command can be safely suspended without corrupting data.

42. The system as set forth in claim 39, wherein said interrupt start code comprises instructions which, when executed, place power sources and read/write circuitry in a state for use during execution of the operation corresponding to the next command.

43. The system as set forth in claim 39, wherein said interrupt start code comprises instructions which, when executed, performs a context switch of the state of the array controller with respect to the operation corresponding to the current command and the operation corresponding to the next command.

44. The system as set forth in claim 33, wherein the algorithm comprises interrupt return code, said interrupt return code executed at the completion of execution of the operation corresponding to the next command.

45. The system as set forth in claim 44, wherein said interrupt return code causes execution of the operation corresponding to the current command to continue at a safe return point in the operation corresponding to the interrupted current command.

46. The system as set forth in claim 43, wherein said array controller further comprises a program counter which points to an instruction to be executed, said interrupt return code adjusting the program counter to point to an instruction at which to continue execution of the operation corresponding to the current command.

47. The system as set forth in claim 44, wherein said interrupt return code comprises instructions which, when executed, place power sources and read/write circuitry in a state for use during execution of the operation corresponding to the current command.

48. The system as set forth in claim 45, wherein safe return point varies according to the state of execution of the current process when an interrupt is issued.

49. The system as set forth in claim 33, wherein the algorithm determines whether the next command is of a higher priority to interrupt the current command.

50. The system as set forth in claim 31, wherein the current command comprises a command to erase at least a portion of the flash memory array and the next command comprises a command to program at least a portion of the flash memory array, said flash memory system performing a program during erase operation.

51. The system as set forth in claim 31, wherein the user interface comprises a plurality of block status registers indicating a status of a corresponding block, at least one register allocated to each block of the flash memory array, said system executing the current command on a first set comprising at least one block of the flash memory array and executing the next command on a second set comprising at least one block of the flash memory array, said execution of the current command causing the update of corresponding block status registers, said execution of the next command causing the update of the corresponding block status registers, wherein the issuance of the interrupt and the execution of the next command prior to completion of the current command and the corresponding update of the block status registers provides for multiple process execution by a single array controller.

52. A flash memory array system fabricated on a single substrate and coupled to a processing means comprising:

an interrupt status means, which when set, permits issuance of an interrupt during the execution of a command;

receiving means coupled to the processing means for receiving from the processing means commands to be executed by the flash memory and having storage to store the received commands including the current command executing and means for issuing an interrupt signal if the interrupt status means is set and the storage comprises the current command executing and a next command to be executed;

executing means coupled to the receiving means to receive operations to execute, said executing means controlling power sources to read, erase and program the flash memory array, said executing means coupled to receive the interrupt signal issued by the receiving means;

storage means coupled to the executing means to store a state of the executing means;

upon receipt of the interrupt signal, said executing means placing the flash memory array in a predetermined state, saving the state of the executing means, executing operations corresponding to the next command, restoring the state of the array controller stored in the storage means, and continuing execution of operations corresponding to the current command;

such that interrupts can be processed by the flash memory system without corrupting the flash memory arrays.

53. The system as set forth in claim 52, further comprising at least one algorithm which is executed by the executing means in response to an operation to execute.

54. The system as set forth in claim 53, wherein the algorithm indicates whether the algorithm can be interrupted.

55. The system as set forth in claim 53, wherein the algorithm comprises instructions to be executed, said code including instructions to enable and disable interrupts such that during certain instructions interrupts are prohibited.

56. The system as set forth in claim 55, wherein said instructions comprise an enable interrupt instruction (ENI) which sets the interrupt status means and identifies an instruction at which the operation corresponding to the current command is to continue execution after execution of the operation corresponding to the next command.

57. The system as set forth in claim 56, wherein said instructions comprises a disable interrupt instruction (DSI) which resets the interrupt status means.

58. The system as set forth in claim 56, wherein said array controller further comprises an interrupt return register, said interrupt return register storing the identification of the instruction at which the operation corresponding to the current command is to continue execution after execution of the operation corresponding to the next command.

59. The system as set forth in claim 53, wherein the algorithm comprises interrupt start code, said interrupt start code executed when an interrupt is issued.

60. The system as set forth in claim 59, further comprising a means for identifying the location of the interrupt start code and an algorithm comprising an instruction which, when executed, sets the means to identify the location of the interrupt start code.

61. The system as set forth in claim 59, wherein said interrupt start code comprises instructions which are executed in response to an interrupt, said instructions identifying a point during execution of the operation corresponding to the command at which the operation can be safely suspended without corrupting data.

62. The system as set forth in claim 59, wherein said interrupt start code comprises instructions which, when executed, place power sources and read/write circuitry for the flash memory array in a state for use during execution of the operation corresponding to the next command.

63. The system as set forth in claim 59, wherein said interrupt start code comprises instructions which, when executed, performs a context switch of the state of the array controller with respect to the operation corresponding to the current command and the operation corresponding to the next command.

64. The system as set forth in claim 53, wherein an algorithm comprises interrupt return code, said interrupt return code executed at the completion of execution of the operation corresponding to the next command.

65. The system as set forth in claim 54, wherein said interrupt return code causes execution of the operation corresponding to the current command to continue at a safe return point in the interrupted operation corresponding to the current command.

66. The system as set forth in claim 64, wherein said interrupt return code comprises instructions which, when executed, place power sources and read/write circuitry in a state for use during execution of the operation corresponding to the current command.

67. The system as set forth in claim 65, wherein the safe return point varies according to the state of execution of the current process when an interrupt is issued.

68. The system as set forth in claim 53, wherein the algorithm determines whether the operation corresponding to the next command is of a higher priority to interrupt the current command.

69. The system as set forth in claim 52, wherein the current command comprises a command to erase at least a portion of the flash memory array and the next command comprises a command to program at least a portion of the flash memory array, said flash memory system performing a program during erase operation.

70. The system as set forth in claim 52, further comprising a means for storing a status of blocks of the flash memory array, said executing means executing the current command on at a first set of blocks of the flash memory array comprising at least one block and executing the next command on a second set of blocks of the flash memory array comprising at least one block, said execution of the current command causing the update of the means for storing the status of blocks, said execution of the next command causing the update of the means for storing a status of blocks, wherein the issuance of the interrupt and the execution of the next command prior to completion of the current command and the update of the means for storing a status of blocks provides for multiple process execution by a single array controller.

71. In a flash memory array system coupled to a processing device, said system comprising at least one flash memory array, a command queue and an array controller for performing operations on the array, a method performed by the flash memory system for processing interrupts of execution of operations on the flash memory array without corrupting the flash memory array, said method comprising the steps of:

receiving from the processing device commands to be executed by the flash memory array system;

executing a current command to perform operations on the flash memory array;

storing the received commands in said command queue having storage to store the received of commands including the current command executing;

providing interrupt status, which when set to a first state, permits issuance of an interrupt during the execution of a command;

if the interrupt status is set and the command queue comprises the current command executing and a next command to be executed,

saving the state of the array controller in at least one register,

executing the next command,

restoring the state of the array controller stored in the register, and

continuing execution of the current command;

such that interrupts can be processed by the flash memory system without intervention from the processing device and without corrupting the flash arrays.

72. The method as set forth in claim 71, further comprising the step of providing at least one algorithm comprising instructions which are executed when executing a command.

73. The method as set forth in claim 72, further comprising the step of determining whether the current command executing can be interrupted.

74. The method as set forth in claim 73, wherein the step of determining comprises the steps of executing instructions to enable interrupts and executing instructions to disable interrupts during execution of the command such that interrupt during execution of certain instructions are prohibited.

75. The method as set forth in claim 74, wherein said step of executing instructions to enable interrupts comprises the steps of setting the interrupt status and identifying an instruction in the algorithm at which to continue execution of the current command after execution of the next command.

76. The method as set forth in claim. 71, further comprising the step of identifying a point during execution of the current command at which the current command can be safely suspended without corrupting data if the interrupt status is set and the command queue comprises the current command executing and a next command to be executed.

77. The method as set forth in claim 71, further comprising the step of placing power sources and read/write circuitry in a state for use during execution of the next command if the interrupt status is set and the command queue comprises the current command executing and a next command to be executed.

78. The method as set forth in claim 72, wherein the step of continuing execution of the current command comprises the step of causing execution of the current command to continue at a safe return point in the interrupted current command.

79. The method as set forth in claim 72, further comprising the step of placing power sources and read/write circuitry in a state for use during execution of the current command prior to the step of continuing execution of the current command.

80. The method as set forth in claim 73, wherein the step of determining comprises the step of identifying whether the next command is of a higher priority to interrupt the current command.

81. The method as set forth in claim 71, wherein the step of executing the current command comprises the step of erasing at least a portion of the flash memory array and the step of executing the next command comprises the step of programming at least a portion of the flash memory array, such that said method performs a program during erase operation.

82. The method as set forth in claim 71, further comprising the step of providing a plurality of block status registers indicating a status of the corresponding block of the flash memory array, said step of executing the current command comprising the step of updating at least one corresponding block status register, said step of executing the next command comprising the step of updating at least one corresponding block status register, wherein the issuance of the interrupt and the execution of the next command prior to completion of the current command and the corresponding update of the block status registers provides for multiple process execution by a single array controller.

83. A system comprising:

a processor for issuing commands;

a bus coupled to the processor;

a flash memory system fabricated on a single substrate and coupled to the bus comprising;

a flash array comprising a plurality of flash cells for storage of data;

a user interface for receiving commands from the processor to be executed by the flash memory system, said user interface comprising a command queue having storage to store the received commands and logic that generates a program memory address identifying the location of code in a program memory which, when executed, performs the command;

an array controller coupled to the user interface to receive the program memory address, said array controller comprising a micro-controller and the program memory, said program memory being programmable by a user to comprise code that is selectively executed by the microcontroller, said program memory address identifying the location of the code in the program memory the micro-controller is the execute, said micro-controller performing operations with respect to the flash array in accordance with the code in program memory;

wherein the flash memory system can be programmed to perform a plurality of functions to be performed by the micro-controller, increasing the flexibility of the flash memory system and off loading control of the flash array from the processor onto the micro-controller.

84. The system as set forth in claim 83, wherein said user interface further comprises a command state machine, said command state machine receiving commands to be executed and initiating the array controller to receive the command address and execute code to perform the command issued by the processor.

85. The system as set forth in claim 83, said user interface further comprising a jump table identifying an offset vector for each command to be executed by the array controller into the program memory of the array controller, said offset vector indicating the location of code to be executed in response to the command issued by the processor.

86. The system as set forth in claim 85, wherein the offset vector points to an index location in the program memory, said index location identifying the first address of the code to be executed from the program memory by the array controller.

87. The system as set forth in claim 86, wherein the jump table is configured to map multiple commands to a single offset vector to permit multiple classes of commands, distinguished by the hardware configuration of the flash memory system, to utilize the same code, thereby supporting multiple hardware configurations without modification of the user interface or array controller.

88. The system as set forth in claim 87, wherein the user interface generates at least one hardware configuration signal to the array controller in conjunction with the transmission of the offset vector to identify different hardware configurations.

89. The system as set forth in claim 86, wherein code executed in response to a command can be changed by modifying the starting address stored in the index location to reference a different portion of the program memory.

90. The system as set forth in claim 83, wherein said system further comprising at least one page buffer for receiving and temporarily storing code to be executed by the array controller to perform an update of the program memory, such that if a command is received by the user interface to update the program memory, said user interface causing the array controller to execute the code temporarily stored in the page buffer to update the program memory, wherein the code executed pursuant to a specific command can be modified or code corresponding to additional commands can be added.

91. The system as set forth in claim 83, wherein said commands comprise commands to program and erase the flash array.

92. A flash memory system fabricated on a single substrate comprising:

a flash array comprising a plurality of flash cells for storage of data;

receiving means for receiving commands to be executed by the flash memory system;

command means for generating a program memory address identifying the location of code in a program memory means which, when executed, performs the command;

execution means coupled to receive the program memory address, said execution means comprising the program memory means, said program memory means being programmable by a user to comprise code that is selectively executed by the execution means, said program memory address identifying the location of the code in program memory means the execution means is to execute, said execution means performing operations with respect to the flash memory array in accordance with the code in program memory;

wherein the flash memory system can be programmed to perform a plurality of functions to be performed by the execution means, increasing the flexibility of the flash memory system and off loading control of the flash array onto the execution means.

93. The system as set forth in claim 92, wherein said receiving means further comprises a means for initiating the execution means to receive the program memory address and execute code to perform the command.

94. The system as set forth in claim 92, said command means further comprising a jump table identifying an offset vector for each command to be executed by the execution means into the program memory of the execution means, said offset vector indicating the location of code to be executed in response to the command.

95. The system as set forth in claim 94, wherein the offset vector points to an index location in the program memory, said index location identifying the starting address of the code to be executed from the program memory by the execution means.

96. The system as set forth in claim 95, wherein the jump table is configured to map multiple commands to a single offset vector to permit multiple classes of commands, distinguished by the hardware configuration of the flash memory system, to utilize the same code, thereby supporting multiple hardware configurations without modification of the flash memory system.

97. The system as set forth in claim 96, wherein the command means generates at least one hardware configuration signal to the execution means in conjunction with the transmission of the offset vector to identify different hardware configurations.

98. The system as set forth in claim 95, wherein code executed in response to a command can be changed by modifying the starting address stored in the index location to reference a different portion of the program memory.

99. The system as set forth in claim 92, wherein said system further comprises a memory means for receiving and temporarily storing code to be executed by the execution means to perform an update of the program memory, such that if a command is received by the receiving means to update the program memory, said command means causing the array controller to execute the code temporarily stored in the memory means to update the program memory, wherein the code executed pursuant to a specific command can be modified or code corresponding to additional commands can be added.

100. The system as set forth in claim 92, wherein said commands comprise commands to program and erase the flash array.

101. In a flash memory array system implemented as a single substrate comprising at least one flash memory array, logic and a command queue, a method performed by the flash memory array system for performing a plurality of programmable commands comprising the steps of:

receiving from a coupled processing device commands to be executed by the flash memory system;

providing a program memory comprising at least one section of code;

generating a program memory address in response to the command received identifying a location of code in program memory which, the code, when executed, performs a command received from the processing device; and

executing the code starting at the location identified by the program memory address.

102. The method as set forth in claim 101, further comprising the steps of providing a jump table identifying an offset vector into the program memory of the array controller for each command to be executed, said offset vector indicating the location of code in the program memory to be executed in response to the received command.

103. The method as set forth in claim 102, wherein the offset vector points to an index location in the program memory, said index location identifying a starting address of the code to be executed from the program memory.

104. The method as set forth in claim 103, further comprising the step of configuring the jump table to map multiple commands to a single offset vector to permit multiple classes of commands, distinguished by the hardware configuration of the flash memory system, to utilize the same code, thereby supporting multiple hardware configurations without modification of the flash memory system.

105. The method as set forth in claim 104, further comprising the step of generating at least one hardware configuration signal in conjunction with the transmission of the offset vector to identify different hardware configurations.

106. The method as set forth in claim 103, wherein code executed in response to a command can be changed by modifying the starting address stored in the index location to reference a different portion of the program memory.

107. The method as set forth in claim 101, further comprising the steps of:

receiving code to be executed to perform an update of the program memory;

temporarily storing the received code;

receiving a command to update the program memory; and

updating the program memory by executing the code temporarily stored;

wherein the code executed pursuant to a specific command can be modified or code corresponding to additional commands can be added to the program memory.

108. The method as set forth in claim 101, wherein said commands comprise commands to program and erase the flash array.