Fabrication of w-polycide-to-poly capacitors with high linearity
First Claim
1. An integrated circuit in and on a silicon substrate having polycide-to-polysilicon capacitors and metal oxide silicon field effect devices with polycide gates, which are separated from each other by means of field oxide regions, comprising:
- field oxide regions, n-well and p-well regions, and gate oxide regions located in and on said silicon substrate;
said polycide-to-polysilicon capacitors are located on the surface of said field oxide regions, whereinsaid polycide-to-polysilicon capacitors comprise an ion-implanted polycide bottom plate having an upper layer of silicide over a lower doped layer of polysilicon;
an interpoly oxidation layer over said bottom plate, which acts as a dielectric for said polycide-to-polysilicon capacitor;
a second doped polysilicon layer located on said interpoly oxidation layer, which forms the top plate of said polycide-to-polysilicon capacitor; and
remaining layers to complete said integrated circuit, including dielectric layers, a metallization system connecting said metal oxide silicon field effect device and said polycide-to-polysilicon capacitor to other parts of said integrated circuit, and a passivation layer over said metallization system.
0 Assignments
0 Petitions
Accused Products
Abstract
A method of forming a polycide-to-polysilicon capacitor with a low voltage coefficient and high linearity is described. A a first layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the substrate and the field oxide regions. A layer of silicide is deposited over the polysilicon layer. The layer of silicide and the layer of polysilicon on the field oxide region are patterned, to form a polycide bottom plate of the capacitor. The polycide bottom plate is annealed. Sidewalls are formed on the sides of the polycide bottom plate. The polycide bottom plate is ion implanted in a vertical to produce the low voltage coefficient and high linearity. An interpoly dielectric layer is formed and patterned on the surface of the polycide bottom plate to act as a dielectric for the polycide-to-polysilicon capacitor. The interpoly dielectric layer is densified. A second layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the dielectric layer and on the surface of the substrate and the field oxide regions. The second layer of polysilicon is patterned to form the top plate of the capacitor.
20 Citations
20 Claims
-
1. An integrated circuit in and on a silicon substrate having polycide-to-polysilicon capacitors and metal oxide silicon field effect devices with polycide gates, which are separated from each other by means of field oxide regions, comprising:
-
field oxide regions, n-well and p-well regions, and gate oxide regions located in and on said silicon substrate; said polycide-to-polysilicon capacitors are located on the surface of said field oxide regions, wherein said polycide-to-polysilicon capacitors comprise an ion-implanted polycide bottom plate having an upper layer of silicide over a lower doped layer of polysilicon; an interpoly oxidation layer over said bottom plate, which acts as a dielectric for said polycide-to-polysilicon capacitor; a second doped polysilicon layer located on said interpoly oxidation layer, which forms the top plate of said polycide-to-polysilicon capacitor; and
remaining layers to complete said integrated circuit, including dielectric layers, a metallization system connecting said metal oxide silicon field effect device and said polycide-to-polysilicon capacitor to other parts of said integrated circuit, and a passivation layer over said metallization system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A polycide-to-polysilicon capacitor, comprising:
-
an ion-implanted polycide bottom plate having an upper layer of silicide over a lower doped layer of polysilicon; an interpoly oxidation layer over said bottom plate, which acts as a dielectric for said polycide-to-polysilicon capacitor; and a second doped polysilicon layer located on said interpoly oxidation layer, which forms the top plate of said polycide-to-polysilicon capacitor. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification