High speed comparator having two differential amplifier stages and latch stage

• US 5,510,734 A
• Filed: 06/14/1995
• Issued: 04/23/1996
• Est. Priority Date: 06/14/1994
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sone, Kazuya
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/490,174
• Time in Patent Office: 314 Days
• Field of Search: 327/63-67, 327/77-79, 327/55, 327/87, 327/89, 327/91, 327/95, 327/96, 327/97, 327/202, 327/203, 327/204, 327/199, 327/214, 327/223
• US Class Current: 327/65
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration

Abstract

In a comparator including a first differential amplifier stage for amplifying the difference in potential between input signals, a second differential amplifier stage for amplifying the difference in potential between output signals of the first differential amplifier stage, and a latch stage for positively feeding output signals of the second amplifier stage back thereto, a first differential switch circuit alternately activates the second differential amplifier stage and the latch stage, and a second differential switch circuit alternately activates the first differential amplifier stage and the latch stage.

Claims

1. A comparator comprising:

a first differential amplifier stage for receiving first and second input signals and amplifying the difference in potential therebetween to generate first and second differential signals;

a second differential amplifier stage, connected to said first differential amplifier stage, for receiving said first and second differential signals and amplifying the difference in potential therebetween to generate third and fourth differential signals;

a latch stage, connected to said second differential amplifier stage, for positively feeding said third and fourth differential signals back to said second differential amplifier to latch said third and fourth differential signals;

a first differential switch circuit, connected to said second differential stage and said latch stage, for alternately activating said second differential amplifier stage and said latch stage; and

a second differential switch circuit, connected to said first differential stage and said latch stage, for alternately activating said first differential stage and said latch stage.

2. A comparator as set forth in claim 1, wherein said first differential switch circuit activates said second differential amplifier stage when said second differential switch circuit activates said first differential stage,

said first differential switch circuit activating said latch stage when said second differential switch circuit activates said latch stage.

3. A comparator as set forth in claim 1, wherein said first differential amplifier stage comprises:

first and second resistors connected to a first power supply terminal;

a first transistor, connected between said first resistor and said second differential switch circuit and being controlled by said first input signal to generate said first differential signal; and

a second transistor, connected between said second resistor and said second differential switch circuit and being controlled by said second input signal to generate said second differential signal.

4. A comparator as set forth in claim 1, wherein said second differential amplifier stage comprises:

third and fourth resistors connected to a first power supply terminal;

a third transistor, connected between said third resistor and said first differential switch circuit and being controlled by said second differential signal to generate said third differential signal; and

a fourth transistor, connected between said fourth resistor and said first differential switch circuit and being controlled by said first differential signal to generate said fourth differential signal.

5. A comparator asset forth in claim 1, wherein said latch stage comprises:

fifth and sixth resistors connected to a first power supply terminal;

a fifth transistor, connected between said fifth resistor and said first and second differential switch circuits and being controlled by said fourth differential signal to control said third differential signal; and

a sixth transistor, connected between said sixth resistor and said first and second differential switch circuits and being controlled by said third differential signal to control said fourth differential signal.

6. A comparator as set forth in claim 1, wherein said first differential switch circuit comprises:

a seventh transistor connected to said second differential amplifier stage and being controlled by a first control signal;

an eighth transistor connected to said latch stage and being controlled by a second control signal opposite in phase to said first control signal; and

a first constant current source connected to said-seventh and eighth transistors and to a second power supply terminal.

7. A comparator as set forth in claim 1, wherein said second differential switch circuit comprises:

a ninth transistor connected to said first differential amplifier stage and being controlled by a first control signal;

a tenth transistor connected to said latch stage and being controlled by a second control signal opposite in phase to said first control signal; and

a second constant current source connected to said ninth and tenth transistors and to a second power supply terminal.

8. A comparator as set forth in claim 1, wherein said first differential switch circuit comprises:

a seventh transistor connected to said second differential amplifier stage and being controlled by a first control signal; and

an eighth transistor connected to said latch stage and being controlled by a second control signal opposite in phase to said first control signal, and

wherein said second differential switch circuit comprises;

a ninth transistor connected to said first differential amplifier stage and being controlled by said first control signal; and

a tenth transistor connected to said latch stage and being controlled by said second control signal,

said comparator further comprising a constant current source connected to said seventh, eighth, ninth and tenth transistors and to said second power supply terminal.

9. A comparator as set forth in claim 8, wherein said eighth and tenth transistors are replaced by a single transistor.

10. A comparator as set forth in claim 1, further comprising a buffer circuit between said second differential amplifier stage and said latch stage.

11. A comparator comprising:

first and second power supply terminals;

first, second, third and fourth resistors connected to said first power supply terminal;

a first transistor having a collector connected to said first resistor, a base for receiving a first input signal, and an emitter;

a second transistor having a collector connected to said second resistor, a base for receiving a second input signal, and an emitter;

a third transistor having a collector connected to said third resistor, a base connected to said second resistor, and an emitter;

a fourth transistor having a collector connected to said fourth resistor, a base connected to said first resistor, and an emitter;

a fifth transistor having a collector connected to said third resistor, a base connected to said fourth resistor, and an emitter;

a sixth transistor having a connector connected to said fourth resistor, a base collected to said third resistor, and an emitter;

a seventh transistor having a collector connected to the emitters of said first and second transistors, a base for receiving a first control signal, and an emitter;

an eighth transistor having a collector connected to the emitters of said third and fourth transistors, a base for receiving said first control signal;

a ninth transistor having a collector connected to the emitters of said fifth and sixth transistors, a base for receiving a second control signal opposite in phase to said first control signal, and an emitter;

a tenth transistor having a collector connected to the emitters of said fifth and sixth transistors, a base for receiving said second control signal, and an emitter;

a first constant current source connected to the emitters of said seventh and tenth transistors and to said second power supply terminal; and

a second constant current source connected to the emitters of said eighth and ninth transistors and to said second power supply terminal.

12. A comparator as set forth in claim 11, further comprising:

an eleventh transistor having a collector connected to said first power supply terminal, a base connected to said third resistor, and an emitter connected to the base of said fifth transistor,

a twelfth transistor having a collector connected to said first power supply terminal, a base connected to said fourth resistor, and an emitter connected to the base of said sixth transistor;

a third constant current source connected between the emitter of said eleventh transistor and said second power supply terminal; and

a fourth constant current source connected between the emitter of said twelfth transistor and said second power supply terminal.

13. A comparator comprising:

first and second power supply terminals;

first, second, third and fourth resistors connected to said first power supply terminal;

a first transistor having a collector connected to said first resistor, a base for receiving a first input signal, and an emitter;

a second transistor having a collector connected to said second resistor, a base for receiving a second input signal, and an emitter;

a third transistor having a collector connected to said third resistor, a base connected to said second resistor, and an emitter;

a fourth transistor having a collector connected to said fourth resistor, a base connected to said first resistor, and an emitter;

a fifth transistor having a collector connected to said third resistor, a base connected to said fourth resistor, and an emitter;

a sixth transistor having a collector connected to said fourth resistor, a base connected to said third resistor, and an emitter;

a seventh transistor having a collector connected to the emitters of said first and second transistors, a base for receiving a first control signal, and an emitter;

an eighth transistor having a collector connected to the emitters of said third and fourth transistors, a base for receiving said first control signal;

a ninth transistor having a collector connected to the emitters of said fifth and sixth transistors, a base for receiving a second control signal opposite in phase to said first control signal, and an emitter;

a tenth transistor having a collector connected to the emitters of said fifth and sixth transistors, a base for receiving said second control signal, and an emitter; and

a constant current source connected to the emitters of said seventh, eighth, ninth and tenth transistors and to said second power supply terminal.

14. A comparator comprising:

first and second power supply terminals;

first, second, third and fourth resistors connected to said first power supply terminal;

a first transistor having a collector connected to said first resistor, a base for receiving a first input signal, and an emitter;

a second transistor having a collector connected to said second resistor, a base for receiving a second input signal, and an emitter;

a third transistor having a collector connected to said third resistor, a base connected to said second resistor, and an emitter;

a fourth transistor having a collector connected to said fourth resistor, a base connected to said first resistor, and an emitter;

a fifth transistor having a collector connected to said third resistor, a base connected to said fourth resistor, and an emitter;

a sixth transistor having a collector connected to said fourth resistor, a base connected to said third resistor, and an emitter;

a seventh transistor having a collector connected to the emitters of said first and second transistors, a base for receiving a first control signal, and an emitter;

an eighth transistor having a collector connected to the emitters of said third and fourth transistors, a base for receiving said first control signal;

a ninth transistor having a collector connected to the emitters of said fifth and sixth transistors, a base for receiving a second control signal opposite in phase to said first control signal, and an emitter; and

a constant current source connected to the emitters of said seventh, eighth and ninth transistors and to said second power supply terminal.

15. A comparator comprising:

first and second power supply terminals;

first, second, third and fourth resistors connected to said first power supply terminal;

a first transistor having a drain connected to said first resistor, a gate for receiving a first input signal, and a source;

a second transistor having a drain connected to said second resistor, a gate for receiving a second input signal, and a source;

a third transistor having a drain connected to said third resistor, a gate connected to said second resistor, and a source;

a fourth transistor having a drain connected to said fourth resistor, a gate connected to said first resistor, and a source;

a fifth transistor having a drain connected to said third resistor, a gate connected to said fourth resistor, and a source;

a sixth transistor having a drain connected to said fourth resistor, a gate connected to said third resistor, and a source;

a seventh transistor having a drain connected to the sources of said first and second transistors, a gate for receiving a first control signal, and a source;

an eighth transistor having a drain connected to the sources of said third and fourth transistors, a gate for receiving said first control signal;

a ninth transistor having a drain connected to the sources of said fifth and sixth transistors, a gate for receiving a second control signal opposite in phase to said first control signal, and a source;

a tenth transistor having a drain connected to the sources of said fifth and sixth transistors, a gate for receiving said second control signal, and a source;

a first constant current source connected to the sources of said seventh and tenth transistors and to said second power supply terminal; and

a second constant current source connected to the sources of said eighth and ninth transistors and to said second power supply terminal.

16. A comparator as set forth in claim 15, further comprising:

an eleventh transistor having a drain connected to said first power supply terminal, a gate connected to said third resistor and a source connected to the gate of said fifth transistor,

a twelfth transistor having a drain connected to said first power supply terminal, a gate connected to said fourth resistor, and a source connected to the gate of said sixth transistor;

a third constant current source connected between the source of said eleventh transistor and said second power supply terminal; and

a fourth constant current source connected between the source of said twelfth transistor and said second power supply terminal.

17. A comparator comprising:

first and second power supply terminals;

first, second, third and fourth resistors connected to said first power supply terminal;

a first transistor having a drain connected to said first resistor, a gate for receiving a first input signal, and a source;

a second transistor having a drain connected to said second resistor, a gate for receiving a second input signal, and a source,

a third transistor having a drain connected to said third resistor, a gate connected to said second resistor, and a source;

a fourth transistor having a drain connected to said fourth resistor, a gate connected to said first resistor, and a source;

a fifth transistor having a drain connected to said third resistor, a gate connected to said fourth resistor, and a source;

a sixth transistor having a drain connected to said fourth resistor, a gate connected to said third resistor, and a source;

a seventh transistor having a drain connected to the sources of said first and second transistors, a gate for receiving a first control signal, and a source;

an eighth transistor having a drain connected to the emitters of said third and fourth transistors, a gate for receiving said first control signal;

a ninth transistor having a drain connected to the sources of said fifth and sixth transistors, a gate for receiving a second control signal opposite in phase to said first control signal, and a source;

a tenth transistor having a drain connected to the sources of said fifth and sixth transistors, a gate for receiving said second control signal, and a source; and

a constant current source connected to the sources of said seventh, eighth, ninth and tenth transistors and to said second power supply terminal.

18. A comparator comprising:

first and second power supply terminals;

first, second, third and fourth resistors connected to said first power supply terminal;

a first transistor having a drain connected to said first resistor, a gate for receiving a first input signal, and a source;

a second transistor having a drain connected to said second resistor, a gate for receiving a second input signal, and a source,

a third transistor having a drain connected to said third resistor, a gate connected to said second resistor, and a source;

a fourth transistor having a drain connected to said fourth resistor, a gate connected to said first resistor, and a source;

a fifth transistor having a drain connected to said third resistor, a gate connected to said fourth resistor, and a source;

a sixth transistor having a drain connected to said fourth resistor, a gate connected to said third resistor, and a source;

a seventh transistor having a drain connected to the sources of said first and second transistors, a gate for receiving a first control signal, and a source;

an eighth transistor having a drain connected to the sources of said third and fourth transistors, a gate for receiving said first control signal;

a ninth transistor having a drain connected to the sources of said fifth and sixth transistors, a gate for receiving a second control signal opposite in phase to said first control signal, and a source; and

a constant current source connected to the sources of said seventh, eighth and ninth transistors and to said second power supply terminal.