Circuitry and method for clamping a boost signal
First Claim
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1. A semiconductor device, comprising:
- a power supply voltage node receiving a power supply voltage;
boosting means for generating on a boost line a boost potential having a level higher than said power supply voltage;
clamping means for restricting an upper limit of the potential on said boost line to the sum of the power supply voltage and one of a plurality of clamping levels; and
clamping level control means for selecting a clamping level of said clamping means.
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Abstract
A clamping circuit clamping a boost signal supplied on a boost line includes a p-channel MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. p-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented.
59 Citations
22 Claims
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1. A semiconductor device, comprising:
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a power supply voltage node receiving a power supply voltage; boosting means for generating on a boost line a boost potential having a level higher than said power supply voltage; clamping means for restricting an upper limit of the potential on said boost line to the sum of the power supply voltage and one of a plurality of clamping levels; and clamping level control means for selecting a clamping level of said clamping means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 18)
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14. A semiconductor device, comprising:
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an external power supply voltage node receiving an external power supply voltage; a power supply voltage-down means for down-converting the external power supply voltage from said external power supply voltage node for generating an internal power supply voltage and an internal power supply voltage node; boosting means receiving the internal power supply voltage from said internal power supply voltage node for outputting a boost potential higher than said internal power supply voltage on a boost line, and clamping means for restricting an upper limit of the potential of said boost line to the sum of the internal power supply voltage and one of a plurality of clamping levels.
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15. A semiconductor device, comprising:
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clamp control means for rendering active a clamping level control signal when a power supply voltage is at least at a first voltage level during an increase of said power supply voltage, and for rendering inactive said clamping level control signal a predetermined time after said power supply voltage attains said first voltage or less during a decrease of said power supply voltage; and clamping means connected to a boost line boosted to a voltage higher than said power supply voltage and responsive to the clamping level control signal from said clamp control means, for restricting an upper limit of the potential said boost line to the sum of the power supply voltage and one of a plurality of clamping levels, said clamping means including means for selecting a prescribed clamping level and for decreasing said prescribed clamping level when the clamping level control signal from said clamp control means is rendered active.
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16. A semiconductor device, comprising:
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clamp control means for rendering active a clamping level control signal when a power supply voltage is at least at a first voltage during an increase of a power supply voltage, and for rendering said clamping level control signal inactive when said power supply voltage attains a second voltage lower than said first voltage or less during a decrease of said power supply voltage; and clamping means connected to a boost line boosted to a voltage higher than said power supply voltage and responsive to the clamping level control signal from said clamp control means for restricting an upper limit of the potential of said boost line to the sum of the power supply voltage and one of a plurality of clamping levels, said clamping means including means for selecting a prescribed clamping level and for decreasing said prescribed clamping level when the clamping level control signal from said clamp control means is rendered active.
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17. A method for clamping a voltage on a boost line on which a boost signal having a voltage level higher than a power supply voltage supplied to a power supply voltage node is transmitted, comprising the steps of:
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clamping an upper limit of a voltage of said boost line to first level during an overvoltage-applied mode of operation when a voltage applied to said power supply voltage node is set to a voltage higher than that in a normal operation mode; and clamping an upper limit of the voltage of said boost line to a second level when the voltage supplied to said power supply voltage node is equal to the voltage supplied thereto during the normal operation mode, so that a difference between said first level and said power supply voltage is less than that between said second level and said power supply voltage.
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19. A semiconductor device to which is applied a power supply voltage of a first level for operating said semiconductor device in a normal operating mode and to which is applied a power supply voltage of a second level greater than the first level for operating the semiconductor device in a test operating mode, the semiconductor device comprising:
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a power supply voltage node for receiving the power supply voltage of the first or second level; boosting means for applying on a boost line a boost potential of a level higher than the level of the power supply voltage applied on said power supply voltage node; clamping means for restricting an upper limit of the potential of boost line to the sum of the power supply voltage and one of a plurality of clamping levels; and clamping control means, responsive to a signal for operating said semiconductor device in the test mode for selecting a clamping level of said clamping means. - View Dependent Claims (20, 21)
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22. A semiconductor device comprising:
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a power supply voltage node receiving a power supply voltage; a boost node receiving a boosted voltage higher than the voltage on said power supply voltage node, an n channel insulated gate transistor having one conduction terminal and a control gate connected together to said boost node, and another conduction terminal; a p channel insulated gate type transistor having one conduction terminal coupled to the other conduction terminal of said n channel insulated gate type transistor, another conduction terminal coupled to said power supply voltage node, and a control gate receiving a mode control signal having a high level of said voltage on said power supply voltage node and a low level of a ground level, such that the boost node is clamped at levels above the level of said power supply voltage.
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Specification