Programmable pin configuration logic circuit for providing a chip select signal and related method

• US 5,511,182 A
• Filed: 08/31/1994
• Issued: 04/23/1996
• Est. Priority Date: 08/31/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Jackson, Basil J., Eifert, James B., Le, Chinh H.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/298,638
• Time in Patent Office: 601 Days
• Field of Search: 395/550, 395/775, 395/800
• US Class Current: 713/600
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A pin configuration logic circuit (120) has a pin function register (130) which defines a selected pin function, such as chip enable, write enable, and output enable, to be provided as a chip select signal. The logic circuit (120) allows an arbitrary pipeline length by causing the chip select signal to obey only the timing of the active cycle. For a two-deep access pipeline, the logic circuit (120) marks whether a first or a second cycle owns the pin. The pin configuration logic circuit (120) uses the timing associated with the selected pin function to provide the chip select signal during the first cycle if the attributes of the cycle, such as an access to a region programmed in the pin function register, are met. During the second cycle, the pin configuration logic circuit (120) further obeys the timing associated with the selected pin function if the attributes of that cycle are also met.

Claims

1. A programmable pin configuration logic circuit for providing a chip select signal, comprising:

a programmable pin function register including a first bit field defining a selected chip select pin function of a plurality of chip select pin functions to be provided as the chip select signal;

a first obey logic circuit having a first input for receiving a first cycle start signal, a second input for receiving a first cycle end signal, and an output for providing a first obey signal, said first obey logic circuit activating said first obey signal in response to said first cycle start signal and deactivating said first obey signal in response to said first cycle end signal;

a second obey logic circuit having a first input for receiving a second cycle start signal, a second input for receiving a second cycle end signal, and an output for providing a second obey signal, said second obey logic circuit activating said second obey signal in response to said second cycle start signal and deactivating said second obey signal in response to said second cycle end signal;

a plurality of pin function logic circuits each associated with a corresponding one of said plurality of chip select pin functions;

each pin function logic circuit having first and second control inputs respectively receiving said first and second obey signals, first and second timing inputs receiving first and second timing signals, corresponding to first and second memory access cycles, respectively, and associated with said selected chip select pin function, and an output providing a function output signal;

each pin function logic circuit activating said function output signal thereof in response to said first timing signal when said first obey signal is active and to said second timing signal when said second obey signal is active, when said first bit field selects said corresponding one of said plurality of chip select pin functions; and

an output circuit having a plurality of inputs for receiving said function output signal from each of said plurality of pin function logic circuits, and an output for providing the chip select signal, said output circuit activating the chip select signal in response to an activation of said function output signal of one of said plurality of pin function logic circuits.

2. The programmable pin configuration logic circuit of claim 1, wherein said programmable pin function register further has a second bit field defining a selected one of a plurality of regions associated with said chip select signal, and wherein each of said first and second obey logic circuits further activates a corresponding one of said first and second obey signals only when an input region matches said selected one of said plurality of regions.

3. The programmable pin configuration logic circuit of claim 1, wherein said plurality of chip select pin functions comprises chip enable, write enable, and output enable.

4. The programmable pin configuration logic circuit of claim 3, wherein said programmable pin function register further has a second bit field defining a selected one of a plurality of data bytes associated with said chip select signal, and wherein said output circuit further activates the chip select signal in response to a write enable timing signal only when an input data byte matches said selected one of said plurality of data bytes when said selected chip select pin function is write enable.

5. The programmable pin configuration logic circuit of claim 1, wherein said output circuit performs a logical OR between said function output signal of each of said plurality of pin function logic circuits.

6. A programmable pin configuration logic circuit for providing a chip select signal, comprising:

a programmable pin function register including a bit field defining a selected chip select pin function of a plurality of chip select pin functions;

obey logic means, coupled to said programmable pin function register, for activating a first obey signal during a first pipelined cycle and a second obey signal during a second pipelined cycle; and

pin function output means coupled to said programmable pin function register and to said obey logic means, for activating the chip select signal in response to one of a first plurality of input timing signals corresponding to said selected chip select pin function if said first obey signal is active, and for activating the chip select signal in response to one of a second plurality of input timing signals corresponding to said selected chip select pin function if said second obey signal is active.

7. The programmable pin configuration logic circuit of claim 6, wherein said obey logic means comprises:

a first obey logic circuit having a first input for receiving a first cycle begin signal, a second input for receiving a first cycle end signal, and an output for providing said first obey signal; and

a second obey logic circuit having a first input for receiving a second cycle begin signal, a second input for receiving a second cycle end signal, and an output for providing said second obey signal.

8. The programmable pin configuration logic circuit of claim 6, wherein said programmable pin function register further has a second bit field defining a selected one of a plurality of regions associated with said chip select signal, and wherein said obey logic means further activates said first obey signal only when a first input region corresponding to said first pipelined cycle matches said selected one of said plurality of regions.

9. The programmable pin configuration logic circuit of claim 6, wherein said plurality of chip select pin functions comprises chip enable, write enable, and output enable.

10. The programmable pin configuration logic circuit of claim 9, wherein said programmable pin function register further has a second bit field defining a selected one of a plurality of data bytes associated with said chip select signal, and wherein said pin function output means further activates said chip select signal in response to a write enable timing signal only when an input data byte matches said selected one of said plurality of data bytes when said selected chip select pin function is write enable.

11. A method for providing a chip select signal, comprising the steps of:

defining a selected chip select pin function of a plurality of chip select pin functions;

activating a first obey signal during a first pipelined cycle;

activating a second obey signal during a second pipelined cycle;

activating the chip select signal in response to one of a first plurality of input timing signals corresponding to said selected chip select pin function if said first obey signal is active; and

activating the chip select signal in response to one of a second plurality of input timing signals corresponding to said selected chip select pin function if said second obey signal is active.

12. The method of claim 11, wherein said step of defining said selected chip select pin function comprises the step of defining a selected one of chip enable, write enable, and output enable.

13. The method of claim 11, wherein said step of activating said first obey signal during said first pipelined cycle comprises the steps of:

activating said first obey signal in response to a first cycle start signal; and

deactivating said first obey signal in response to a first cycle end signal.

14. The method of claim 11, wherein said step of activating said second obey signal during said second pipelined cycle comprises the steps of:

activating said second obey signal in response to a second cycle start signal; and

deactivating said second obey signal in response to a second cycle end signal.