Performing system tasks at power-off using system management interrupt

• US 5,511,204 A
• Filed: 09/07/1994
• Issued: 04/23/1996
• Est. Priority Date: 09/07/1994
• Status: Expired due to Term

• Current Assignee: Lenovo PC International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Landry, John M., Crump, Dwayne T., Benson, Paul H. IV, Pancoast, Steven T.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/301,464
• Time in Patent Office: 594 Days
• Field of Search: 395/750, 395/575, 364/707, 365/226, 365/227, 365/228, 365/229, 307/66
• US Class Current: 713/330
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. Prior to causing the power supply to cease providing regulated power to the CPU, the power management processor interrupts the CPU via a system management interrupt. Responsive to being interrupted via the system management interrupt, the CPU performs tasks associated with the power supply imminently ceasing to provide regulated power to the CPU. Such tasks include writing data to non-volatile memory and refreshing an alarm value in the power management processor. The CPU can extend the period of time before the power management processor causes the power supply to cease providing regulated power to the CPU while the CPU performs the necessary tasks.

Claims

1. A computer system comprising:

(a) a CPU capable of executing application program code and BIOS code and having a system management interrupt characterized by being a non-maskable interrupt, the interrupt handler of which cannot be altered by application program code;

(b) a power management processor in circuit communication with said CPU via said system management interrupt and operative to activate said CPU'"'"'s system management interrupt;

(c) a power supply in circuit communication with said CPU and said power management processor comprising circuitry for selectively providing system power from an external source to said computer system responsive to said power management processor, characterized by having a first power supply state and a second power supply state, and further characterized by having circuitry for providing auxiliary power to said power management processor;

(d) a non-volatile storage device in circuit communication with said CPU for storing data;

wherein said first power supply state is characterized by said power supply providing system power to said computer system and auxiliary power to said power management processor from said external source; and

wherein said second power supply state is characterized by said power supply not providing system power to said computer system from said external source and said power supply providing auxiliary power to said power management processor from said external source;

(1) wherein said power management processor is further characterized by causing said power supply to transition from said first power supply state to said second power supply state responsive to at least one of a predetermined set of conditions;

(2) wherein said power management processor is further characterized by interrupting said CPU by activating said CPU'"'"'s system management interrupt prior to causing said power supply to transition from said first power supply state to said second power supply state; and

(3) wherein said CPU is further configured to perform at least one predetermined set of tasks responsive to said power management processor interrupting said CPU via said system management interrupt and prior to said power supply transitioning from said first power supply state to said second power supply state, said at least one predetermined set of tasks including said CPU storing data to said non-volatile storage device.

2. A computer system according to claim 1:

(a) wherein said power management processor is further characterized by comprising a timer that expires after a predetermined time interval;

(b) wherein said power management processor causes said power supply to transition from said second power supply state to said first power supply state responsive to the expiration of said timer; and

(c) wherein said CPU calculates and stores to said power management processor the predetermined time interval.

3. A computer system according to claim 2 wherein said at least one predetermined set of tasks further includes said CPU storing data corresponding to the predetermined time interval to said non-volatile storage device.

4. A computer system according to claim 3 wherein said predetermined time interval comprises a number of time units until said power management processor causes said power supply to transition from said second power supply state to said first power supply state and said data corresponding to said predetermined time interval comprises the absolute time and date said power management processor is scheduled to cause said power supply to transition from said second power supply state to said first power supply state.

5. A computer system according to claim 3 wherein said non-volatile storage device is a battery-backed random access memory.

6. A computer system according to claim 3 wherein said non-volatile storage device is a fixed disk storage device.

7. A computer system according to claim 6 wherein said data written to said non-volatile storage device by said CPU comprises data relating to the allocation of system resources.

8. A computer system according to claim 6 wherein said at least one predetermined set of tasks performed by said CPU further comprises causing the state of said computer system to be written to said non-volatile storage device.

9. A computer system according to claim 6 wherein said data written to said non-volatile storage device by said CPU comprises data relating to which power supply state the power supply should default.

10. A computer system according to claim 1 wherein said CPU and said power management processor are characterized in that responsive to being interrupted via said system management interrupt said CPU can prevent for a period of time said power management processor from causing said power supply to transition from said first power supply state to said second power supply state while said CPU performs the at least one predetermined set of tasks.

11. A computer system according to claim 1 wherein said non-volatile storage device is a battery-backed random access memory.

12. A computer system according to claim 1 wherein said non-volatile storage device is a fixed disk storage device.

13. A computer system according to claim 12 wherein said data written to said non-volatile storage device by said CPU comprises data relating to the allocation of system resources.

14. A computer system according to claim 12 wherein said data written to said non-volatile storage device by said CPU comprises data relating to which power supply state the power supply should default.