Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths
First Claim
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1. A data processing apparatus comprising:
- a first (k×
m)-bit data bus for transmitting data of (k×
m)-bits in parallel wherein k and m are an integer larger than one;
at least one (k×
m)-bit I/O peripheral device connected to said first (k×
m)-bit data bus;
a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k×
m)-bit data bus into k data buses having an equal width of data bus;
a plurality of m-bit I/O peripheral devices each of which is connected to one m-bit data bus belonging to said first m-bit data bus group;
a second (k×
m)-bit data bus;
a (k×
m)-bit I/O central processing unit connected to said second (k×
m)-bit data bus;
a second m-bit data bus group consisting of (k+1)-th to k-th m-bit data buses obtained by dividing said second (k×
m)-bit data bus into k data buses having an equal width of data bus;
a transmission control means for generating control signals responsive to a demand of data transmission from said CPU; and
a data path switching means connected between said first m-bit data bus group and second m-bit data bus group which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices, said at least one (k×
m)-bit I/O peripheral device and said CPU in response to a control signal output from said transmission control means.
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Abstract
A data processing apparatus includes a first (k×m)-bit data bus wherein k is a byte count and m is a bit length of one byte, a plurality of m-bit I/O peripheral devices at least one which is connected to two or more of m-bit data buses belonging to a first group consisting of first to k-th m-bit data buses obtained by dividing the first (k×m)-bit data bus into the first to k-th m-bit data buses; a second (k×m)-bit data bus, a (k×m)-bit I/O central processing unit connected to the second (k×m)-bit data bus which is divided into (k+1)-th m-bit data buses consisting of a second group of m-bit data buses; a data path switching circuit connected between the first and second (k×m)-bit data buses which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices and the CPU, and a transmission control circuit for generating control signals responsive to a demand of data transmission from said CPU. The m-bit I/O peripheral devices, first and second data buses, data path switching circuit and transmission control circuit can be integrated on an extended board.
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Citations
13 Claims
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1. A data processing apparatus comprising:
-
a first (k×
m)-bit data bus for transmitting data of (k×
m)-bits in parallel wherein k and m are an integer larger than one;at least one (k×
m)-bit I/O peripheral device connected to said first (k×
m)-bit data bus;a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k×
m)-bit data bus into k data buses having an equal width of data bus;a plurality of m-bit I/O peripheral devices each of which is connected to one m-bit data bus belonging to said first m-bit data bus group; a second (k×
m)-bit data bus;a (k×
m)-bit I/O central processing unit connected to said second (k×
m)-bit data bus;a second m-bit data bus group consisting of (k+1)-th to k-th m-bit data buses obtained by dividing said second (k×
m)-bit data bus into k data buses having an equal width of data bus;a transmission control means for generating control signals responsive to a demand of data transmission from said CPU; and a data path switching means connected between said first m-bit data bus group and second m-bit data bus group which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices, said at least one (k×
m)-bit I/O peripheral device and said CPU in response to a control signal output from said transmission control means. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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2. A data processing apparatus comprising:
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a first (k×
m)-bit data bus for transmitting data of (k×
m)-bits in parallel wherein k and m are an integer larger than oneat least one (k×
m)-bit I/O peripheral device connected to said first (k×
m)-bit data bus;a first m-bit data bus group consisting of first to k-th m-bit data buses obtained by dividing said first (k×
m)-bit data bus into k data buses having an equal width of data bus;a plurality of m-bit I/O data bus belonging to said first m-bit data bus group; a second (k×
m)-bit data bus;a (k×
m)-bit I/O central processing unit connected to said second (k×
m)-bit data bus;a data path switching means connected between said first and second m-bit data bus groups which comprises a first group of m-bit bus transceivers each connecting one m-bit data bus belonging to said first group and a corresponding m-bit data bus belonging to said second group and a second group m-bit bus transceivers each connecting two m-bit data buses belonging to said second group; and a transmission control means for generating control signals responsive to a data transmission demand from said CPU and for selectively controlling said m-bit bus transceivers belonging to said first and second transceiver groups and said m-bit I/O peripheral devices corresponding to the control signals, thereby forming at least one data transmission path between two arbitrary devices selected from among said m-bit I/O peripheral devices, at least one (k×
m)-bit I/O peripheral device and said CPU. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification
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Current AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsTsujimoto, Taizou
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Primary Examiner(s)Lee, Thomas C.
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Assistant Examiner(s)Kim, Sang Hui
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Application NumberUS07/944,442Time in Patent Office1,317 DaysField of Search395/275, 395/200, 395/325, 395/800, 395/851US Class Current710/31CPC Class CodesG06F 13/4018 with data-width conversionG09G 5/363 Graphics controllersG09G 5/39 Control of the bit-mapped m...Y02D 10/00 Energy efficient computing,...
