Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits

• US 5,512,397 A
• Filed: 11/02/1993
• Issued: 04/30/1996
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Duda, Kathleen
• Application Number:
  US08/146,470
• Time in Patent Office: 910 Days
• Field of Search: 430/30, 430/311, 430/313, 430/319, 430/327, 430/394, 430/396
• US Class Current: 430/30
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

Large scale integrated circuits are fabricated using redundant circuit elements to replace defective circuit elements by discretionary interconnect changes as determined by fine-grain testing of the integrated circuits after the logic units (such as individual transistors or logic gates) are fabricated and before they are electrically interconnected. The redundant circuit elements are then interconnected to non-defective circuit elements by one of two methods. In the first method a stepper-scanner apparatus modified to expose most of a resist layer defines the interconnect circuitry, but is shuttered-off over the discretionary interconnect changes. Then the discretionary interconnect changes are exposed by a conventional direct write on wafer pattern generation apparatus. In the second method, the interconnect patterning is accomplished by first fabricating a fixed custom mask defining the interconnect layer for a particular lot size (such as 100) of wafers. The fixed mask is fabricated after each wafer of the lot has been tested, and incorporates all the discretionary changes required to avoid interconnection to each defective circuit element in each of the wafers. The fixed custom mask is then used to expose the resist layer defining the interconnect circuitry for each of the 100 wafers.

Claims

1. A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on a principal surface of a substrate;

forming a resist layer overlying the integrated circuit logic elements;

testing each logic element and determining the presence of defects in each logic element;

determining the location and dimensions of each defect;

providing a fixed mask;

exposing said resist layer with a first exposure through said fixed mask to define electrical interconnects between the logic elements on said resist layer and leaving predetermined portions of said resist layer unexposed, wherein said predetermined portions left unexposed are defined by the location and dimensions of each defect;

exposing said resist layer with a second exposure to define electrical interconnects between the logic elements on said resist layer by exposing only the predetermined portions left unexposed in the preceding step; and

interconnecting the logic elements according to the first and second exposures, thereby excluding the logic elements having defects from the interconnected logic elements.

2. The method of claim 1, wherein the step of exposing the resist layer with a first exposure includes the steps of:

scanning said resist layer in a plurality of scans of variable width; and

interrupting the scanning at the predetermined portions, thereby leaving those predetermined portions unexposed.

3. The method of claim 2, wherein the steps of scanning and interrupting are performed by a stepper scanner modified to avoid exposing the predetermined portions corresponding to the defects as determined in the step of testing.

4. The method of claim 2, wherein the scans are of one widths about 1 to 5 mils.

5. The method of claim 1, wherein the step of exposing the resist layer with a second exposure comprises the step of:

using a direct write on wafer pattern generation tool to pattern the predetermined portions.

6. The method of claim 1 wherein each of said plurality of integrated circuit logic elements is a logic gate.

7. The method of claim 1 wherein each of said plurality of integrated circuit logic elements is a transistor.

8. The method of claim 1 wherein each defect is in a region of less than about 100 μ

m by about 100 μ

m.

9. The method of claim 1 wherein each defect is in a region of diameter less than about 100 μ

m.

10. The method of claim 1 wherein the step of testing each logic element includes the step of fine grain testing.

11. A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on each of a plurality of substrates;

testing each logic element on each substrate to determine the presence of defects in each logic element and the location of each defect;

fabricating at least one fixed mask for the plurality of substrates, the fixed mask defining a fixed pattern to avoid patterning on logic elements including the defects on each substrate; and

forming said fixed pattern on a conductive layer of each substrate as defined by the fixed mask, thereby interconnecting the logic elements and excluding from the interconnection all the logic elements which include defects.

12. The method of claim 11, wherein the step of fabricating at least one fixed mask includes fabricating one fixed mask for defining vias.

13. The method of claim 11 wherein the step of fabricating at least one fixed mask includes fabricating one fixed mask defining a metallization layer.

14. The method of claim 11 wherein each of said plurality of integrated circuit logic elements is a logic gate.

15. The method of claim 11 wherein each of said plurality of integrated circuit logic elements is a transistor.

16. The method of claim 11 wherein each defect is in a region of less than about 100 μ

m by about 100 μ

m.

17. The method of claim 11 wherein each defect is in a region of diameter less than about 100 μ

m.

18. The method of claim 11 wherein the step of testing each logic element includes the step of fine grain testing.

19. A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on a substrate;

testing each logic element and determining the presence of defects in each logic element;

determining the location and dimensions of each defect;

providing a fixed mask;

exposing the substrate with a first exposure through said fixed mask to define electrical interconnects between the logic elements on a surface of the substrate, said first exposure being performed by scanning the fixed mask in a plurality of scans of variable width;

selectively interrupting the scanning thereby leaving predetermined portions of the surface of the substrate unexposed, wherein said predetermined portions left unexposed are defined by the location and dimensions of each defect;

then, exposing the substrate with a second exposure in the predetermined portions left unexposed in the preceding step; and

interconnecting the logic elements according to the first and second exposures, thereby excluding the defects from the interconnected logic elements.

20. A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on a substrate;

testing each logic element and determining the presence of defects in each logic element;

determining the location and dimensions of each defect;

providing a fixed mask;

defining electrical interconnects between the logic elements on a surface of the substrate with a first exposure by scanning the fixed mask in a plurality of scans of variable width using a stepper scanner modified to avoid exposing predetermined portions of the substrate corresponding to the defects as determined in the step of testing;

selectively interrupting the scanning thereby leaving the predetermined portions of the surface of the substrate unexposed, wherein the predetermined portions left unexposed are defined by the location and dimensions of each defect and the interrupting is performed by the modified stepper scanner;

exposing the substrate with a second exposure in the predetermined portions left unexposed in the preceding step; and

interconnecting the logic elements according to the first and second exposures, thereby excluding the defects from the interconnected logic elements.

21. A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on a substrate;

testing each logic element and determining the presence of defects in each logic element;

determining the location and dimensions of each defect;

providing a fixed mask;

defining electrical interconnects between the logic elements on a surface of the substrate with a first exposure by scanning the fixed mask in a plurality of scans of widths of about 1 to 5 mils;

selectively interrupting the scanning thereby leaving the predetermined portions of the surface of the substrate unexposed, wherein the predetermined portions left unexposed are defined by the location and dimensions of each defect;

exposing the substrate with a second exposure in the predetermined portions left unexposed in the preceding step; and

interconnecting the logic elements according to the first and second exposures, thereby excluding the defects from the interconnected logic elements.

22. A method of fabricating integrated circuits comprising the steps of:

fabricating a plurality of integrated circuit logic elements on a substrate;

testing each logic element and determining the presence of defects in each logic element;

determining the location and dimensions of each defect;

providing a fixed mask;

defining electrical interconnects between the logic elements on a surface of the substrate by scanning the fixed mask, and leaving predetermined portions of the surface of the substrate unscanned, wherein the predetermined portions left unscanned are defined by the location and dimensions of each defect;

imaging the predetermined portions left unscanned in the preceding step using a direct write on wafer pattern generation tool; and

interconnecting the logic elements according to the scanning of the fixed mask and the imaging using the direct write on wafer pattern generation tool, thereby excluding the defects from the interconnected logic elements.