Clock recovery phase locked loop control using clock difference detection and forced low frequency startup
First Claim
1. A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) comprising:
- (a) providing a sequence of data pulses and a sequence of reference clock pulses,(b) resetting the phase locked loop to force the VCO to its lowest operating frequency,(c) releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses,(d) detecting the presence of data pulse transitions,(e) in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and(f) outputting output clock pulses from the phase locked loop.
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Abstract
A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) is comprised of providing a sequence of data pulses and a sequence of reference clock pulses, resetting the phase locked loop to force the VCO to its lowest operating frequency, releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, detecting the presence of data pulse transitions, in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and outputting output clock pulses from the phase locked loop.
87 Citations
14 Claims
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1. A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) comprising:
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(a) providing a sequence of data pulses and a sequence of reference clock pulses, (b) resetting the phase locked loop to force the VCO to its lowest operating frequency, (c) releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, (d) detecting the presence of data pulse transitions, (e) in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and (f) outputting output clock pulses from the phase locked loop. - View Dependent Claims (2, 3, 4, 5, 6)
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7. Apparatus for generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) comprising:
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(a) means for providing a sequence of data pulses and a sequence of reference clock pulses, (b) means for resetting the phase locked loop to force the VCO to its lowest operating frequency, (c) means for releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, (d) means for detecting the presence of transitions of the data pulses, (e) means for forcing the VCO to lock to the data pulses in the event of detection of data pulse transitions, and (f) means for outputting output clock pulses from the phase locked loop. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A clock recovery circuit comprising:
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(a) a digital phase locked loop including, in series, a voltage controlled oscillator, a mode divider connected to the output of the oscillator, a first phase detector connected to the output of the mode divider and a loop filter for receiving an output signal of the phase detector and providing an output signal to the oscillator, (b) means for applying a digital input signal to another input of the phase detector, whereby the phase detector provides an output signal representing the phase difference between the digital input signal and an output signal of the mode divider, (c) a reference clock signal input, (d) a second phase detector for receiving the reference clock signal at an input thereof, (e) a reference divider for receiving an output signal of the oscillator and for generating a DCLK signal, (f) means for applying the DCLK signal to another input of the second phase detector, (g) a clock difference detector for receiving the DCLK signal, the reference clock signal and an output signal of the mode divider and for generating an out-of-range signal in the event the DCLK and reference clock signals differ by a predetermined number of pulses from the output of the mode divider, (h) a multiplexer for passing an output signal of either of the phase detectors to the loop filter, (i) a state machine for receiving the out-of-range signal and for controlling the multiplexer to pass the output signal of the second phase detector to the loop filter in the event of the presence of an out-of-range signal, and to pass the output signal of the first phase detector to the loop filter in the absence of the out-of-range signal. - View Dependent Claims (14)
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Specification