Digital oversampled quadrature modulator
First Claim
1. A circuit providing phase shifted signals, said circuit comprising:
- one or more first input terminals for receiving first digital data to be modulated, said first digital data having a maximum value, a minimum value, and a mid-value approximately equal to an average of said maximum value and said minimum value;
one or more inverters having inputs coupled to receive said first digital data to be modulated, said inverters outputting inverted data;
a first multiplexer having as inputs at least said inverted data, a value equal to said mid-value, and non-inverted data;
a first counter providing at least a four-state control signal to said first multiplexer for selecting as an output of said first multiplexer said inverted data, said mid-value, or said non-inverted data; and
a sampling clock controlling said first counter, wherein an output of said first multiplexer provides a first modulated carrier signal having a carrier frequency of less than or equal to one-fourth that of said sampling clock.
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Accused Products
Abstract
The preferred embodiment modem is an all hardware modulator which receives as its input two baseband drive signals, I and Q, which can come from a ROM filter or any other digital filter. Instead of storing modem responses in a ROM, multiplexers for the I and Q channels are used in combination with a control circuit to essentially perform as sine/cosine modulators for the baseband signal. The inputs into the I channel multiplexer include a non-inverted I signal, an inverted I signal, and a mid-value signal. The Q channel multiplexer has applied to it a non-inverted Q signal, an inverted Q signal, and a mid-value Q signal. Two-bit counters are applied to the control terminals of the I and Q multiplexers, where the 2-bit counters are clocked by a sample frequency. In one embodiment, the sample frequency is chosen to be four times the carrier frequency. The counter for the Q channel begins one count behind the I channel counter, thus giving a 90° phase shift for the Q channel. The outputs of the two multiplexers are added to provide the output of the digital modem. The resulting word is then applied to a digital-to-analog converter and subsequently up-converted, filtered, and amplified for transmission.
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Citations
20 Claims
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1. A circuit providing phase shifted signals, said circuit comprising:
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one or more first input terminals for receiving first digital data to be modulated, said first digital data having a maximum value, a minimum value, and a mid-value approximately equal to an average of said maximum value and said minimum value; one or more inverters having inputs coupled to receive said first digital data to be modulated, said inverters outputting inverted data; a first multiplexer having as inputs at least said inverted data, a value equal to said mid-value, and non-inverted data; a first counter providing at least a four-state control signal to said first multiplexer for selecting as an output of said first multiplexer said inverted data, said mid-value, or said non-inverted data; and a sampling clock controlling said first counter, wherein an output of said first multiplexer provides a first modulated carrier signal having a carrier frequency of less than or equal to one-fourth that of said sampling clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for providing phase shifted signals, said method comprising the steps of:
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generating first digital data to be modulated, said first digital data having a maximum value, a minimum value, and a mid-value approximately equal to an average of said maximum value and said minimum value; inverting said first digital data to be modulated to created inverted data; applying said inverted data, said mid-value, and non-inverted data to inputs of a first multiplexer; controlling said first multiplexer with a first counter providing at least a four-state control signal to said first multiplexer for selecting as an output of said first multiplexer said inverted data, said mid-value, or said non-inverted data; and clocking said first counter with a sampling clock to cause an output of said first multiplexer to provide a first modulated carrier signal having a carrier frequency of less than or equal to one-fourth that of said sampling clock. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification