Hierarchical floorplanner for gate array design layout

• US 5,513,119 A
• Filed: 06/21/1995
• Issued: 04/30/1996
• Est. Priority Date: 08/10/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Semiconductor America, Inc. (Mitsubishi Electric Corporation)
• Inventors: Moore, Wesley, Huffman, Ward
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/493,016
• Time in Patent Office: 314 Days
• Field of Search: 364/491, 364/490, 364/489, 364/488
• US Class Current: 716/119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A set of logic cells is hierarchically grouped to form groups to be placed on an integrated circuit for gate array layout. A user interface allows a user to interact with a placement system. The system is supplied with input design files defining the integrated circuit, the cells to be grouped, the groups to be placed, and input/output buffers to be placed on the perimeter of the integrated circuit for connecting the groups with external circuitry. The system reads the input design files to create a database used for placing desired input/output buffers and for hierarchically grouping the cells and placing the groups. The groups are defined by their size, determined using utilization and aspect ratio values of the areas where the cells are to be placed. The user is allowed to move the buffers and groups to any valid locations within the integrated circuit.

Claims

1. A placement system controlled by a user for hierarchically grouping a plurality of design elements into groups and selecting their positions on a design area, comprising:

means responsive to input information for creating a database defining said design elements and said design area,

means responsive to said database for enabling said user to select positions of input/output terminals on said design area for connecting said design elements within said design area with circuitry outside said design area,

means responsive to said database for determining, prior to the placement of the design elements, the size of regions on said design area to be occupied by said groups of design elements, based on the number of basic cells in each of the groups and the area of one of the basic cells,

means responsive to the determined size of said regions and the selected positions of the input/output terminals for enabling said user to place said groups on said design area.

2. The placement system of claim 1 further comprising means for forming output data defining the selected positions of said groups and said input/output terminals.

3. The placement system of claim 1, wherein said means for determining the size of regions comprises means for defining the group based on the number of design elements in the group and the utilization ratio of a region where the group is to be positioned.

4. The placement system of claim 1, wherein said means for determining the size of regions comprises means for defining the group based on the number of design elements in the group and the aspect ratio of a region where the group is to be positioned.

5. The placement system of claim 1, wherein said means for placing the groups comprises means for locating each of the groups within a region defined by its aspect ratio.

6. The placement system of claim 1, wherein said means for placing the groups comprises means for locating the design elements for each of the groups at a selected location on said design area within a region defined by its aspect ratio.

7. The placement system of claim 1, wherein said means for selecting positions of input/output terminals comprises means responsive to said database for displaying input/output buffers used for transferring signals in and out of the design area and means for placing the displayed input/output buffers at a predetermined position with respect to pins of an integrated circuit defined by said design area.

8. A method of placing a plurality of design elements on an integrated circuit using a placement system, said method comprising the steps of:

supplying the placement system with input information to define said design elements and said integrated circuit,

enabling a user to select positions of input/output terminals on said integrated circuit for connecting said design elements on said integrated circuit with external circuitry based on said input information,

hierarchically grouping said design elements into a plurality of groups,

prior to the placement of the design elements, determining the size of regions on said integrated circuit to be occupied by said groups using said input information, based on the number of basic cells in each of the groups and the area of one of the basic cells,

enabling the user to place said groups on said integrated circuit based on the determined size of said regions and the selected positions of the input/output terminals.

9. The method of claim 8 further comprising the step of forming output data defining the selected positions of said groups and said input/output terminals.

10. The method of claim 8, wherein said step of determining the size of regions comprising the step of defining the group based on the number of design elements in the group and the utilization ratio of a region where the group is to be placed.

11. The method of claim 8, wherein said step of determining the size of regions comprising the step of defining the group based on the number of design elements in the group and the aspect ratio of a region where the group is to be placed.

12. The method of claim 8, wherein said step of placing the groups comprising the step of locating each of the groups within a region defined by its aspect ratio.

13. The method of claim 8, wherein said step of placing the groups comprising means for locating the design elements for each of the groups at a selected location on said design area within a region defined by its aspect ratio.

14. The method of claim 8, wherein said step of selecting positions of input/output terminals comprising the step of displaying input/output buffers used for transferring signals in and out of the design area and the step of moving the displayed input/output buffers to a predetermined position with respect to pins of an integrated circuit defined by said design area.

15. In an element placement system having a display for visualizing layout of an integrated circuit comprising a plurality of logic cells, a method for grouping said logic cells comprising the steps of:

supplying the placement system with input information to define said logic cells and said integrated circuit,

combining said logic cells into a plurality of groups defined by the size of an area on said integrated circuit to be occupied by each group, the size of said area being determined prior to the placement of the logic cells, based on the size of said logic cells in the group and the number of the logic cells in the group,

displaying said plurality of groups and said integrated circuit on said display,

moving said plurality of groups to selected positions on said integrated circuit.

16. The method of claim 15, wherein the size of said area is determined based on its aspect ratio.

17. The method of claim 16, wherein the size of said area is determined based on its utilization ratio.

18. The method of claim 15, wherein each of said groups is placed in a selected region having a predetermined aspect ratio.

19. The method of claim 18, wherein each of said groups is moved within said selected region.

20. A placement system controlled by a user for hierarchically grouping a plurality of design elements into groups and selecting their positions on a design area, comprising:

means responsive to input information for creating a database defining said design elements and said design area,

means responsive to said database for enabling said user to select positions of input/output terminals on said design area for connecting said design elements within said design area with circuitry outside said design area,

means responsive to said database for determining, prior to the placement of the design elements, the size of regions on said design area to be occupied by said groups of design elements, based on the number of basic cells in each of the groups and the area of one of the basic cells,

means responsive to the determined size of said regions and the selected positions of the input/output terminals for indicating to said user places of said groups on said design area.