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Logic placement using positionally asymmetrical partitioning method

  • US 5,513,124 A
  • Filed: 03/12/1993
  • Issued: 04/30/1996
  • Est. Priority Date: 10/30/1991
  • Status: Expired due to Term
First Claim
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1. A partitioning method for placing a circuit design into a programmable integrated circuit device having a distribution of physical resources along a horizontal or vertical line, the circuit design comprising a plurality of circuit elements, some of which are to be distributed to said physical resources along a horizontal or vertical line, the method comprising:

  • identifying specific circuit elements of the plurality of circuit elements to be placed along a horizontal or vertical line;

    attaching weights to lines connected to said circuit elements identified as elements to be placed along a horizontal or vertical line, said weights related to the disadvantage of placing said elements on opposite sides of a cut line parallel to said horizontal or vertical line; and

    partitioning the plurality of circuit elements according to a min-cut procedure such that a cost of crossing said cut line is determined using those of said weights which are attached to lines crossing said cut line.

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