Circuit and method for determining the operating performance of an integrated circuit

• US 5,513,152 A
• Filed: 06/22/1994
• Issued: 04/30/1996
• Est. Priority Date: 06/22/1994
• Status: Expired due to Term

• Current Assignee: Teradata US, Inc. (Teradata Corporation)
• Original Assignee: AT&T Global Information Solutions Company (NCR Voyix Corporation)
• Inventors: Cabaniss, Frank W.
• Primary Examiner(s): Miska, Vit W.
• Application Number:
  US08/263,628
• Time in Patent Office: 678 Days
• Field of Search: 368/113, 368/117-120, 324/617, 327/250, 327/252, 364/569, 395/425, 395/550
• US Class Current: 368/118
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22

Abstract

A circuit and method for determining the operating performance of an integrated circuit which may be used to screen integrated circuits prior to sale or delivery, or to optimize the frequency of the integrated circuit during use. The circuit employs a comparison circuit to compare a first time of arrival of a clock pulse, which is propagating through the integrated circuit with a second time of arrival of the clock signal at a second input. The comparison circuit produces an output signal which may be used to reject or accept the integrated circuit, or to automatically adjust the frequency to minimize the delay.

Claims

1. A circuit for determining the operating performance of an integrated circuit comprising:

a clock circuit which produces a clock signal;

a first signal path through the integrated circuit and coupled at a first end to the clock circuit;

a second signal path through the integrated circuit and coupled at a first end to the clock circuit; and

a comparison circuit having first and second inputs coupled at second ends of the first and second signal paths for determining a time delay between the clock signal along the first signal path and the clock signal along the second signal path.

2. The circuit as recited in claim 1, wherein the first signal path provides the most delay.

3. The circuit as recited in claim 1, wherein the second signal path provides the most delay.

4. The circuit as recited in claim 1, wherein the clock circuit operates at a single frequency.

5. The circuit as recited in claim 1, wherein the clock circuit is tunable to a plurality of frequencies.

6. The circuit as recited in claim 1, wherein the clock circuit comprises a voltage-controlled oscillator.

7. The circuit as recited in claim 1, wherein the comparison circuit comprises a D-type flip-flop.

8. The circuit as recited in claim 6, further comprising:

a feedback circuit between the comparison circuit and the voltage-controlled oscillator for minimizing the delay between the first and second signal paths;

wherein the output signal of the comparison circuit has a first polarity when the clock signal at the first input of the comparison circuit arrives before the clock signal arrives at the second input of the comparison circuit, and has a polarity opposite to the first polarity when the clock signal at the first input of the comparison circuit arrives after the clock signal arrives at the second input of the comparison circuit.

9. The circuit as recited in claim 8, further comprising:

an indicator circuit coupled to the output of the comparison circuit.

10. The apparatus as recited in claim 9, wherein the indicator circuit comprises:

a warning light.

11. The apparatus as recited in claim 8, wherein the feedback circuit comprises:

an analog control circuit which stabilizes the frequency of the clock signal from the voltage-controlled oscillator.

12. The circuit as recited in claim 11, wherein the analog control circuit comprises:

a first resistor coupled to the output of the comparison circuit;

a capacitor coupled to the first resistor and to a ground; and

a second resistor coupled in parallel with the capacitor.

13. The apparatus as recited in claim 1, further comprising:

a third signal path through the integrated circuit and coupled at a first end to the clock circuit;

an OR gate having first and second inputs and an output;

wherein the output of the OR gate is coupled to the first input of the comparison circuit;

wherein the second end of the second signal path is coupled to the first input of the OR gate; and

wherein a second end of the third signal path is coupled to the second input of the OR gate.

14. A circuit for determining the operating performance of an integrated circuit comprising:

a single frequency clock circuit which produces a clock signal;

a first signal path through the integrated circuit and coupled at a first end to the clock circuit;

a second signal path through the integrated circuit and coupled at a first end to the clock circuit;

a D-type flip-flop, having first and second inputs coupled at second ends of the first and second signal paths and an output, for determining a time delay between the clock signal along the first signal path and the clock signal along the second signal path; and

a delay monitoring circuit coupled to the output of the D-type flip-flop.

15. A circuit for optimizing the operating performance of an integrated circuit comprising:

a voltage-controlled oscillator which produces a clock signal;

a first signal path through the integrated circuit and coupled at a first end to the voltage-controlled oscillator;

a second signal path through the integrated circuit and coupled at a first end to the voltage-controlled oscillator;

a D-type flip-flop, having first and second inputs coupled at second ends of the first and second signal paths and an output, for determining a time delay between the clock signal along the first signal path and the clock signal along the second signal path; and

a feedback circuit between the D-type flip-flip and the voltage-controlled oscillator for minimizing the delay between the first and second signal paths;

wherein the output signal of the D-type flip-flip has a first polarity when the clock signal at the first input of the D-type flip-flip arrives before the clock signal arrives at the second input of the D-type flip-flip, and has a polarity opposite to the first polarity when the clock signal at the first input of the D-type flip-flip arrives after the clock signal arrives at the second input of the D-type flip-flip.

16. The apparatus as recited in claim 15, wherein the feedback circuit comprises:

an analog control circuit which stabilizes the frequency of the clock signal from the voltage-controlled oscillator.

17. A method for determining the operating performance of an integrated circuit comprising the steps of:

(a) coupling a clock signal from a clock circuit to a signal path through the integrated circuit, wherein the signal path terminates at a first input of a comparison circuit;

(b) coupling the clock signal to a second input of the comparison circuit; and

(c) comparing a first time of arrival of a clock pulse at the first input with a second time of arrival at the second input by the comparison circuit.

18. The method as recited in claim 17, further comprising the step of:

(d) generating an output signal by the comparison signal containing the result of step (c).

19. The method as recited in claim 18, further comprising the steps of:

(e) rejecting the integrated circuit if the delay is greater than a predetermined threshold; and

(f) accepting the integrated circuit if the delay is below the threshold.

20. The method as recited in claim 17, further comprising the steps of:

(d) feeding back a signal from the comparison device to the clock circuit to decrease the clock signal frequency if the first time of arrival is after the second time of arrival by the clock frequency control circuit and increase the clock signal frequency if the first time of arrival is before the second time of arrival.