Apparatus and method for transmitting information with a subminimally modulated transmission signal

• US 5,513,219 A
• Filed: 08/26/1994
• Issued: 04/30/1996
• Est. Priority Date: 08/26/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Ronald Ham
• Original Assignee: Compaq Computer Corporation (HP Inc.), Ronald E. Ham
• Inventors: Ham, Ronald E.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/296,721
• Time in Patent Office: 613 Days
• Field of Search: 375/271, 375/272, 375/274, 375/278, 375/302, 375/303, 375/305, 375/322, 375/334, 375/335, 375/336, 332/117, 332/123, 332/124, 332/100, 329/300, 329/318, 329/315, 455/42, 455/44, 455/205, 455/214, 455/110, 455/112
• US Class Current: 375/272
• CPC Class Codes: H04L 27/122 using digital generation of carrier signals digital function generators G06F1/02, H04L17/10; generating pulses having stepped portions using digital techniques H03K4/026
• CPC Class Codes: H04L 27/144 with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements

Abstract

Applicant'"'"'s invention includes an apparatus and associated method for transmitting information at a high rate using an undermodulated frequency shift keyed signal. The transmission rate is independent of the data content and the system requires no zero crossing detectors. The demodulator combines non-linear processing circuitry with a conventional demodulator.

Claims

1. Communication system apparatus capable of transmitting information via a frequency modulated signal over a transmission media with bandwidth ≧

f_dev +2 * f_d at transmission rates not achievable using conventional demodulators comprising;

subminimal modulation means capable of generating a phase continuous carrier signal with a modulation index less than 0.5 and wherein the timing of said means is independent of zero crossings or other DC levels of said modulated signal and wherein said means processes data at a constant rate independent of the data content;

FM signal processing and transmission means connected to said modulation means, wherein the carrier signal is transmitted over a transmission media;

FM signal receiving and processing means, configured to receive the carrier wave;

nonlinear signal processing means, connected to said signal receiving and processing means, wherein the modulation index of the carrier signal is increased;

a linear frequency demodulator serially connected to the output of said nonlinear signal processing means;

an analog to digital converter serially connected to the output of said linear frequency demodulator; and

a symbol decoder serially connected to the output lines of said analog to digital converter.

2. The apparatus of claim 1 wherein said nonlinear signal processing means comprises a frequency multiplication circuit.

3. The apparatus of claim 2 wherein said frequency multiplication circuit comprises one or more voltage squaring circuits.

4. The apparatus of claim 3 wherein said voltage squaring circuits is implemented with a Motorola MC1496 or equivalent integrated circuit.

5. The apparatus of claim 1 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

6. The apparatus of claim 5 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

7. The apparatus of claim 6 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

8. The apparatus of claim 7 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.

9. The apparatus of claim 2 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

10. The apparatus of claim 9 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

11. The apparatus of claim 10 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its

address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

12. The apparatus of claim 11 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.

13. The apparatus of claim 3 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

14. The apparatus of claim 13 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

15. The apparatus of claim 14 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter;

16. The apparatus of claim 15 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.

17. The apparatus of claim 4 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

18. The apparatus of claim 17 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

19. The apparatus of claim 18 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

20. The apparatus of claim 19 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits;

21. A method of transmitting information over a media with bandwidth limited to f_dev +2 * f_d via a frequency modulated signal at a higher rate than is achievable using a linear demodulator comprising the steps of:

selecting a communication system comprising;

subminimal modulation means capable of generating a phase continuous carrier signal with a modulation index less than 0.5 and wherein the timing of said means is independent of zero crossings or other DC levels of said modulated signal and wherein said means processes data at a constant rate independent of the data content;

FM signal processing and transmission means connected to said modulation means, wherein the carrier signal is transmitted over a transmission media;

FM signal receiving and processing means, configured to receive the carrier wave;

nonlinear signal processing means, connected to said signal receiving and processing means, wherein the modulation index of the carrier signal is increased;

a frequency demodulator serially connected to the output of said nonlinear signal processing means;

an analog to digital converter serially connected to the output of said linear frequency demodulator; and

a symbol decoder serially connected to the output lines of said analog to digital converter;

generating a phase continuous carrier signal with a with a modulation index less than 0.5 and wherein the timing of said modulation means is independent of zero crossings or other DC levels of said modulated signal and wherein said means processes data at a constant rate independent of the data content;

processing and transmitting said carrier signal over a transmission media with said processing and transmitting means;

receiving and processing said transmitted signal over a transmission media;

increasing the modulation index of said received signal with said nonlinear signal processing means;

demodulating said the output signal of said nonlinear processing means with said frequency demodulator;

converting the analog output of said frequency demodulator to a digital symbol with said analog to digital converter; and

recovering the original data from said digital word with said symbol decoder.

22. The method of claim 21 wherein said nonlinear signal processing means comprises a frequency multiplication circuit.

23. The method of claim 22 wherein said frequency multiplication circuit comprises one or more voltage squaring circuits.

24. The method of claim 23 wherein said voltage squaring circuits is implemented with a Motorola MC1496 or equivalent integrated circuit.

25. The method of claim 21 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

26. The method of claim 25 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

27. The method of claim 26 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

28. The method of claim 27 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.

29. The method of claim 22 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

30. The method of claim 29 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

31. The method of claim 30 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

32. The method of claim 31 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.

33. The method of claim 23 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

34. The method of claim 33 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

35. The method of claim 34 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

36. The method of claim 35 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.

37. The method of claim 24 wherein said subminimal modulation means receives externally supplied serial digital data which controls the frequency of said carrier signal.

38. The method of claim 37 wherein said subminimal modulation means comprises;

an externally supplied data clock;

a serial-to-parallel converter, clocked by said data clock, wherein N bits of externally supplied serial data are converted into a symbol of K parallel bits;

a multi-frequency oscillator, connected to the output of said serial-to-parallel converter, wherein the oscillation frequency is controlled by said K-bit symbol.

39. The method of claim 38 wherein said multi-frequency oscillator comprises,

a high speed system clock;

a divide-by-N circuit supplied by said data clock wherein a clock signal of period N times the period of said data clock is generated;

an accumulator connected to the output of said serial-to-parallel converter and controlled by said system clock such that said K-bit symbol is latched into a first register within said accumulator on positive going transitions of said divide-by-N data clock signal and wherein said accumulator increments the value of an output register by the value of the first register on every positive going transition of said system clock;

a look-up table read only memory (ROM), with its address lines connected to the output register of said accumulator, manufactured or programmed so that the contents of said ROM at any address "x" are equal to sin(x);

a digital to analog converter with its inputs connected to the outputs of said look-up table ROM;

a low pass filter connected to the output of said digital to analog converter.

40. The method of claim 39 wherein;

said high speed system clock operates at a frequency of approximately 75 MHz;

said externally supplied serial data is fed at a rate of approximately 125 Mbits/sec;

N is approximately equal to 5;

K is approximately equal to 32;

the output register of said accumulator is a word of approximately 24 bits;

the output of said ROM is a word of approximately 10 bits.