Watchdog timer for computer system reset

• US 5,513,319 A
• Filed: 06/08/1995
• Issued: 04/30/1996
• Est. Priority Date: 07/02/1993
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Schieve, Eric, Finch, Richard
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US08/488,708
• Time in Patent Office: 327 Days
• Field of Search: 395/185.04, 395/185.08, 395/182.21, 395/183.10, 364/260.8, 364/261.8, 364/267.2, 364/267.9
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A watchdog timer circuit of the present invention monitors a computer system (S) during diagnostic testing and resets the system when it is nonfunctioning. A real-time clock (RTC) (21), programmed by a central processing unit (CPU) (29) to run for a period of time, produces a reset signal after the period of time elapses. Typically this time period relates to a diagnostic program being run. The reset signal serves as an input to reset circuitry (28) which immediately transmits a nonmaskable interrupt (NMI) to the CPU (29) and, after a delay period, transmits a hardware reset signal to the CPU (29). When functioning properly, the CPU (29) prepares for the hardware reset signal that is produced by the reset circuitry (28) and avoids being reset by the hardware reset signal. However, when the CPU (29) is not functioning properly, the hardware reset signal resets the CPU (29). Additional circuitry stores information regarding where the system (S) failed during the diagnostic testing and retrieves such information for the user upon reset. An additional feature resets all of the components within the system (S) upon a CPU (29) reset via power reset circuitry.

Claims

1. A circuit for resetting a nonfunctioning computer system, comprising:

a watchdog timer coupled to a central processing unit (CPU) within said computer system to enable said watchdog timer to receive a start signal from said CPU indicating that said CPU is beginning execution of a particular task, said watchdog timer beginning to measure a preselected period of time upon receipt of said start signal and generating a timeout signal upon expiration of said preselected period of time;

a reset signal generating circuit for receiving said timeout signal from said watchdog timer and providing, in response thereto, a nonmaskable interrupt signal to said CPU and a reset signal; and

a reset circuit coupled to said CPU for receiving the reset signal from the reset signal generating circuit and for transmitting a hardware reset signal to said CPU after a delay period, the delay period allowing said CPU to reset only when said CPU has not responded to the nonmaskable interrupt signal indicating that said CPU is nonfunctioning.

2. The circuit as recited in claim 1 further comprising a circuit for storing data representing whether expiration of said preselected period of time caused said reset of said CPU.

3. The circuit as recited in claim 1 wherein said CPU, after a reset, accesses data representing whether said resetting circuit caused said reset of said CPU.

4. The circuit as recited in claim 1 wherein said preselected period of time is a period of time sufficient to allow said CPU to execute said particular task.

5. The circuit as recited in claim 1 wherein said particular task is a routine for diagnosing a component within said computer system.

6. The circuit as recited in claim 1 wherein said watchdog timer is a real time clock coupled to said CPU.

7. The circuit as recited in claim 1 wherein the hardware reset signal also initiates a power reset of a plurality of components within the computer system other than said CPU.

8. A method of resetting a nonfunctioning computer system, comprising the steps of:

receiving a start signal from a central processing unit (CPU) within said computer system into a watchdog timer, said start signal indicating that said CPU is beginning execution of a particular task;

measuring a preselected period of time with said watchdog timer upon receiving said start signal;

generating a timeout signal with said watchdog timer upon expiration of said preselected period of time;

receiving said timeout signal into a reset circuit coupled to said CPU;

responsive to said timeout signal, transmitting a nonmaskable interrupt signal to said CPU;

determining, upon receipt of the nonmaskable interrupt signal, whether said CPU is nonfunctioning; and

after a delay period, providing, with said reset circuit, a hardware reset signal to said CPU in response to said timeout signal to thereby reset said CPU only when said CPU has not responded to the nonmaskable interrupt signal.

9. The method as recited in claim 8 further comprising the step of storing data representing whether expiration of said preselected period of time caused said reset of said CPU.

10. The method as recited in claim 8 wherein said CPU, after a reset, accesses data representing whether said resetting circuit caused said reset of said CPU.

11. The method as recited in claim 8 wherein said preselected period of time is a period of time sufficient to allow said CPU to execute said particular task.

12. The method as recited in claim 8 wherein said particular task is a routine for diagnosing a component within said computer system.

13. The method as recited in claim 8 wherein said watchdog timer is a real time clock coupled to said CPU.

14. The method as recited in claim 8 further including the step of initiating a power reset of a plurality of system components other than said CPU within said computer system when said CPU is nonfunctioning.

15. A circuit for resetting a nonfunctioning computer system, comprising:

a central processing unit (CPU) for transmitting task identification data concerning a particular task said CPU is about to execute to a storage location within said computer system, said CPU further for transmitting a start signal indicating that said CPU is beginning execution of said particular task;

a watchdog timer for receiving said start signal and measuring a preselected period of time in response thereto, said watchdog timer further for generating a timeout signal upon expiration of said preselected period of time, said timeout signal indicating that said particular task has not been executed successfully;

a reset signal generating circuit for receiving said timeout signal and, in response thereto, transmitting a nonmaskable interrupt signal to said CPU and providing a reset signal to a reset circuit within said CPU, said reset signal generating circuit also for transmitting timeout data to said storage location, said timeout data indicating that expiration of said period of time caused said reset of said CPU; and

a reset circuit within said CPU for receiving said reset signal from the reset signal generating circuit, delaying for a period of time to allow said CPU, responsive to the receipt of the nonmaskable interrupt signal, to avoid a hardware reset when said CPU is functioning properly, and causing a hardware reset of said CPU when said CPU is nonfunctioning.

16. The circuit as recited in claim 15 wherein said CPU, after a reset, accesses said task identification and timeout data.

17. The circuit as recited in claim 15 wherein said preselected period of time is a period of time sufficient to allow said CPU to execute said particular task.

18. The circuit as recited in claim 15 wherein said particular task is a routine for diagnosing a component within a computer system under control of said CPU.

19. The circuit as recited in claim 15 wherein said watchdog timer is a real time clock coupled to said CPU.

20. The circuit as recited in claim 15 wherein the reset circuit also initiates a power reset of components other than said CPU within said computer system when said CPU is nonfunctioning.

21. A method of resetting a nonfunctioning computer system,

comprising:

transmitting task identification data to a storage location within said computer system, the task identification data concerning a particular task a central processing unit (CPU) is about to execute;

transmitting a start signal indicating that said CPU is beginning execution of said particular task from said CPU to a watchdog timer;

receiving said start signal into said watchdog timer;

measuring a preselected period of time in response to receipt of said start signal;

generating a timeout signal with said watchdog timer upon expiration of said preselected period of time, said timeout signal indicating that said particular task has not been executed successfully;

receiving said timeout signal into a reset signal generating circuit, said reset signal generating circuit providing, in response thereto, a reset signal to a reset circuit within said CPU;

receiving the reset signal at the reset circuit within said CPU and attempting to vector said CPU to an error handling routine using a nonmaskable interrupt input;

initiating a hardware reset of said CPU after a delay period when said CPU does not vector to the error handling routine; and

transmitting timeout data from said reset signal generating circuit to said storage location, said timeout data indicating that expiration of said period of time caused said reset of said CPU.

22. The method as recited in claim 21 wherein said CPU, after a reset, accesses said task identification and timeout data.

23. The method as recited in claim 21 wherein said preselected period of time is a period of time sufficient to allow said CPU to execute said particular task.

24. The method as recited in claim 21 wherein said particular task is a routine for diagnosing a component within a computer system under control of said CPU.

25. The method as recited in claim 21 wherein said watchdog timer is a real time clock coupled to said CPU.

26. The method as recited in claim 21 wherein the reset circuit also initiates a power reset of components other than said CPU within said computer system when said CPU is nonfunctioning.

27. A personal computer, comprising:

a microprocessor for transmitting identification data concerning a diagnostic routine to be executed to a storage location within said computer, and for transmitting a start signal indicating that said microprocessor is beginning execution of said diagnostic routine;

a real time clock, coupled to said microprocessor for receiving said start signal, said real time clock beginning to measure a preselected period of time sufficient to allow said microprocessor to execute said diagnostic routine, said real time clock also for generating a timeout signal upon expiration of said preselected period of time, said timeout signal indicating that said particular diagnostic routine has not been executed successfully; and

hardware reset circuitry coupled to said microprocessor for receiving said timeout signal and, in response thereto, providing a nonmaskable interrupt signal to said microprocessor and, after a delay period, a reset signal to said microprocessor to initiate a hardware reset of said personal computer, said microprocessor avoiding a hardware reset of said personal computer only when said personal computer is functioning properly and allowing a reset of said personal computer when said personal computer system is nonfunctioning, said hardware reset circuitry also for transmitting timeout data to said storage location, said timeout data indicating that expiration of said preselected period of time caused said hardware reset of said personal computer.

28. The computer as recited in claim 27 wherein said preselected period of time is adjustable as a function of an expected length of execution time of said diagnostic routine.

29. The computer as recited in claim 27 wherein said microprocessor accesses said identification and timeout data following said hardware reset.

30. A method of diagnosing a personal computer, comprising the steps of:

transmitting identification data to a storage location within said computer, the identification data concerning a diagnostic routine that a microprocessor within said computer is about to execute;

transmitting a start signal indicating that said microprocessor is beginning execution of said diagnostic routine from said microprocessor to a real time clock;

receiving said start signal into said real time clock;

measuring a preselected period of time in response to receipt of said start signal with said real time clock;

generating a timeout signal with said real time clock upon expiration of said preselected period of time, generation of said timeout signal indicating that said diagnostic routine has not been executed successfully;

transmitting a nonmaskable interrupt signal to said microprocessor responsive to said timeout signal;

after a delay period, transmitting a hardware reset signal from said hardware reset circuitry to said microprocessor;

receiving the hardware reset signal in said microprocessor;

resetting said personal computer when said personal computer is nonfunctioning; and

transmitting timeout data from said hardware reset circuitry to said storage location, said timeout data indicating that expiration of said period of time caused said reset of said microprocessor.

31. The method as recited in claim 30 wherein said preselected period of time is adjustable as a function of an expected length of execution time of said diagnostic routine.

32. The method as recited in claim 30 wherein said microprocessor accesses said identification and timeout data following said hardware reset.