Multiprocessor system discharging data in networking apparatus in response to off-line information from receiver-side processor

• US 5,513,321 A
• Filed: 08/24/1993
• Issued: 04/30/1996
• Est. Priority Date: 12/22/1992
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Katori, Masayuki
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US08/110,936
• Time in Patent Office: 980 Days
• Field of Search: 370/60, 370/60.1, 370/61, 395/200, 395/250, 395/325, 395/183.15, 395/200.01, 395/200.11, 395/200.15, 395/200.12, 395/200.13
• US Class Current: 709/234
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A multiprocessor system containing a networking apparatus and a plurality of processors for transferring data through the networking apparatus from one to another of the plurality of processors. At least one receiving-side processor transmits a transfer allowance signal to the networking apparatus when the processor is ready to receive data, and transmits an on-line/off-line signal to the networking apparatus, where the on-line/off-line signal indicates whether the second processor is in an on-line state or off-line state. The networking apparatus includes a data transfer control unit, provided on each route for transferring data, for receiving data transferred from one of transmitting-side processors, temporarily storing the data, and transferring the data to one of the receiving-side processor when the data transfer control unit receives the transfer allowance signal from the second processor; and an off-line state detecting unit for outputting a data discharge control signal to the data transfer control unit when the on-line/off-line signal indicates that the second processor is in the off-line state. The data transfer control unit further contains a data discharge unit for discharging the data temporarily stored in the data transfer control unit in response to the data discharge control signal, regardless of the transfer allowance signal.

Claims

1. A multi-processor system comprising:

a networking apparatus; and

a plurality of processors for transferring data through the networking apparatus from one of the plurality of processors to another of the plurality of processors, wherein

at least one first processor among the plurality of processors comprises transmitting means, connected to the networking apparatus, for transmitting data to the networking apparatus,

at least one second processor among the plurality of processors comprises;

receiving means, connected to the networking apparatus, for receiving data transferred from the networking apparatus,

transfer allowance signal transmitting means for transmitting a transfer allowance signal to the networking apparatus when the receiving means is ready to receive data and the at least one second processor is in an on-line state, and

on-line/off-line signal transmitting means for transmitting an on-line/off-line signal to the networking apparatus, the on-line/off-line signal indicating by a voltage level thereof whether the at least one second processor is in one of the on-line state and an off-line state;

said networking apparatus comprising;

switch means for providing a route for transferring data between each of the at least one first processor and a respective one of the at least one second processor corresponding to each first processor,

data transfer control means, provided corresponding to each of said at least one second processor, on an output side of said switch means and, on each route for transferring data, for receiving from said switch means the data transferred between one of the at least one first processor connected to the route and one of the at least one second processor corresponding to said one of the at least one first processor, temporarily storing the data, and transferring the data to said one of the at least one second processor connected to the route, when the data transfer control means receives the transfer allowance signal from the second processor, and

off-line state detecting means, provided corresponding to each of said data transfer control means, for receiving the on-line/off-line signal, directly from said one of the at least one second processor connected to the route, detecting said voltage level of the on-line/off-line signal, and generating and outputting a data discharge control signal to the data transfer control means, when the on-line/off-line signal indicates that the at least one second processor is in the off-line state; and

the data transfer control means further comprises data discharge means for receiving the data discharge control signal, and for discharging the data temporarily stored in the data transfer control means in response to the data discharge control signal, regardless of the transfer allowance signal.

2. A multi-processor system according to claim 1, wherein the receiving means comprises a buffer memory for temporarily storing the data transferred from the data transfer control means,

the transfer allowance signal transmitting means outputs the transfer allowance signal when the data temporarily stored in the buffer is output therefrom, and

the data transfer control means comprises:

a FIFO memory receiving the data transferred from the at least one first processor connected to the route on which the data transfer control means is provided, for temporarily storing the data, and for outputting the data, and

a counter counting an amount of the data temporarily stored in the buffer memory in the receiving means by incrementing a value of a count thereof when the data is output from the FIFO memory, and decrementing the value of the count when the data transfer control means receives the transfer allowance signal.

3. A multi-processor system according to claim 2, wherein the counter outputs a first control signal is applied to the FIFO memory to make the FIFO memory stop outputting the data to the receiving means, when the count reaches a predetermined count corresponding to a maximum amount of data which can be held in the buffer memory.

4. A multi-processor system according to claim 3, wherein the counter further outputs a second control signal active when the count is equal to zero, and

the off-line state detecting means makes the data discharge control signal active when the second control signal is not active, and the on-line/off-line signal indicates that the second processor is in the off-line state.

5. A multi-processor system according to claim 4, wherein the data discharge control signal is applied to the counter as a countdown control signal which makes the counter decrement the value of the count.

6. A networking apparatus for use in a multiprocessor system comprising a networking apparatus and a plurality of processors for transferring data through the networking apparatus from one of the plurality of processors to another of the plurality of processors, wherein at least one first processor among the plurality of processors transmits the data to the networking apparatus, and at least one second processor among the plurality of processors receives data transferred from the networking apparatus, transmits a transfer allowance signal to the networking apparatus when the at least one second processor is ready to receive data and the at least one second processor is in an on-line state, and transmits an on-line/off-line signal to the networking apparatus, where the on-line/off-line signal indicates, by a voltage level thereof, whether the at least one second processor is in one of the on-line state and an off-line state,

said networking apparatus comprising:

switch means for providing a route for transferring data between each of the at least one first processor, and a respective one of the at least one second processor corresponding to each first processor,

data transfer control means, provided corresponding to each of said at least one second processor, on an output side of said switch means, and on each route for transferring data, for receiving from said switch means the data transferred between one of the at least one first processor connected to the route and one of the at least one second processor corresponding to said one of the at least one first processor, temporarily storing the data, and transferring the data to said one of the at least one second processor connected to the route, when the data transfer control means receives the transfer allowance signal from the second processor, and

off-line state detecting means, provided corresponding to each of said data transfer control means, for receiving an on-line/off-line signal, directly from said one of the at least one second processor connected to the route, detecting said voltage level of the on-line/off-line signal, and generating and outputting a data discharge control signal to the data transfer control means, when the on-line/off-line signal indicates that the at least one second processor is in the off-line state; and

the data transfer control means further comprising data discharge means for receiving the data discharge control signal, and for discharging the data temporarily stored in the data transfer control means in response to the data discharge control signal, regardless of the transfer allowance signal.

7. A networking apparatus according to claim 6, wherein the at least one second processor comprises a buffer memory for temporarily storing the data transferred from the data transfer control means, and outputs the transfer allowance signal when the data temporarily stored in the buffer memory is output therefrom, and

the data transfer control means in the networking apparatus comprises:

a FIFO memory receiving the data transferred from the first processor connected to the route on which the data transfer control means is provided, for temporarily storing the data, and for outputting the data, and

a counter for counting an amount of the data temporarily stored in the buffer memory by incrementing a value of a count thereof when the data is output from the FIFO memory, and decrementing the value of the count when the data transfer control means receives the transfer allowance signal.

8. A networking apparatus according to claim 7, wherein the counter outputs a first control signal applied to the FIFO memory to make the FIFO memory stop outputting the data to the receiving means, when the count reaches a predetermined count corresponding to a maximum amount of data which can be held in the buffer memory.

9. A networking apparatus according to claim 8, wherein the counter further outputs a second control signal active when the count is equal to zero, the off-line state detecting means makes the data discharge control signal active when the second control signal is not active, and the on-line/off-line signal indicates that the second processor is in the off-line state.

10. A networking apparatus according to claim 9, wherein the data discharge control signal is applied to the counter as a countdown control signal which makes the counter decrement the value of the count.