Integrated circuit I/O using a high performance bus interface

• US 5,513,327 A
• Filed: 03/31/1994
• Issued: 04/30/1996
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/222,646
• Time in Patent Office: 761 Days
• Field of Search: 395/325, 395/550, 395/275, 395/425, 395/400, 395/309, 395/432, 365/189.02, 365/189.04, 365/189.05, 365/230.02, 365/230.08
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal.

Claims

1. A dynamic random access memory (DRAM), comprising:

a first circuit for providing a clock signal;

a conductor for coupling the DRAM to a bus; and

a receiver circuit coupled to the conductor and the first circuit, the receiver circuit for latching information received from the conductor in response to a rising edge of the clock signal and a falling edge of the clock signal, wherein the receiver circuit comprises;

a first input receiver coupled to the conductor and the first circuit, the first input receiver for latching information provided by the bus via the conductor in response to the rising edge of the clock signal; and

a second input receiver coupled to the conductor and the first circuit, the second input receiver for latching information from the bus in response to the falling edge of the clock signal.

2. The DRAM of claim 1, wherein the first circuit provides a first clock signal and a second clock signal that is a complement of the first clock signal, the first input receiver being coupled to receive the first clock signal such that the first input receiver latches information in response to a rising edge of the first clock signal, the second input receiver being coupled to receive the second clock signal such that the second input receiver latches information in response to a rising edge of the second clock signal.

3. The DRAM of claim 2, wherein the first circuit provides the first and second clock signals in response to an externally provided clock signal.

4. The DRAM of claim 1, wherein the first circuit provides the clock signal in response to an externally provided clock signal.

5. The DRAM of claim 1, wherein the DRAM further comprises:

a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input;

an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer;

a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to the rising edge of the clock signal; and

a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to the falling edge of the clock signal.

6. The DRAM of claim 5, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.

7. A dynamic random access memory (DRAM), comprising:

a first circuit for providing a clock signal;

a conductor for coupling the DRAM to a bus;

a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input;

an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer;

a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to a rising edge of the clock signal; and

a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to a falling edge of the clock signal.

8. The DRAM of claim 7, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.

9. A memory storage system comprising:

a bus for transferring information;

a first dynamic random access memory (DRAM) coupled to the bus, the first DRAM comprising;

a first circuit for providing a clock signal;

a conductor for coupling the DRAM to the bus;

a receiver circuit coupled to the conductor and the first circuit, the receiver circuit for latching information received from the conductor in response to a rising edge of the clock signal and a falling edge of the clock signal;

the receiver circuit comprising;

a first input receiver coupled to the conductor and the first circuit, the first input receiver for latching information provided by the bus via the conductor in response to the rising edge of the clock signal; and

a second input receiver coupled to the conductor and the first circuit, the second input receiver for latching information from the bus in response to the falling edge of the clock signal.

10. The memory storage system of claim 9, wherein the first circuit provides a first clock signal and a second clock signal that is a complement of the first clock signal, the first input receiver being coupled to receive the first clock signal such that the first input receiver latches information in response to a rising edge of the first clock signal, the second input receiver being coupled to receive the second clock signal such that the second input receiver latches information in response to a rising edge of the second clock signal.

11. The memory storage system of claim 10, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing the first and second clock signals in response to a system clock signal.

12. The memory storage system of claim 9, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing a first clock signal and a second clock signal that is a complement of the first clock in response to the system clock signal.

13. The memory storage system of claim 12, wherein a bus cycle for the bus is divided into an even cycle corresponding to a rising edge of the system clock signal and an odd cycle corresponding to a falling edge of the system clock signal, the memory storage system further comprising:

a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.

14. The memory storage system of claim 13, wherein the master is a processor.

15. The memory storage system of claim 12, wherein a bus cycle for the bus is divided into an even cycle corresponding to a falling edge of the system clock signal and an odd cycle corresponding to a rising edge of the system clock signal, the memory storage system further comprising:

a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.

16. The memory storage system of claim 9, wherein the DRAM further comprises:

a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input;

an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer;

a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to the rising edge of the clock signal; and

a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to the falling edge of the clock signal.

17. The memory storage system of claim 16, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.

18. A memory storage system comprising:

a bus for transferring information;

a first dynamic random access memory (DRAM) coupled to the bus, the first DRAM comprising;

a first circuit for providing a clock signal;

a conductor for coupling the DRAM to the bus;

a multiplexer coupled to the first circuit, the multiplexer having an output, a first input, and a second input;

an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer;

a first output line coupled to the first input of the multiplexer, wherein the multiplexer couples the first output line to the output of the multiplexer in response to a rising edge of the clock signal; and

a second output line coupled to the second input of the multiplexer, wherein the multiplexer couples the second output line to the output of the multiplexer in response to a falling edge of the clock signal.

19. The DRAM of claim 18, wherein the output driver is a field effect transistor including a drain coupled to the conductor, a source coupled to system ground, and a gate coupled to output of the multiplexer, the field effect transistor being switched on and off in response to a state of a selected output line provided by the multiplexer.

20. The memory storage system of claim 18, wherein the first circuit provides a first clock signal and a second clock signal that is a complement of the first clock signal, the multiplexer being coupled to receive the first and second clock signals such that the first output line is selected in response to a rising edge of the first clock signal and the second output line is selected in response to a rising edge of the second clock signal.

21. The memory storage system of claim 20, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing the first and second clock signals in response to a system clock signal.

22. The memory storage system of claim 18, wherein the memory storage system further includes a third circuit for providing a system clock signal, the first circuit being coupled to receive the system clock signal, the first circuit for providing a first clock signal and a second clock signal that is a complement of the first clock in response to the system clock signal.

23. The memory storage system of claim 22, wherein a bus cycle for the bus is divided into an even cycle corresponding to a rising edge of the system clock signal and an odd cycle corresponding to a falling edge of the system clock signal, the memory storage system further comprising:

a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.

24. The memory storage system of claim 23, wherein the master is a processor.

25. The memory storage system of claim 22, wherein a bus cycle for the bus is divided into an even cycle corresponding to a falling edge of the system clock signal and an odd cycle corresponding to a rising edge of the system clock signal, the memory storage system further comprising:

a master coupled to the bus and the third circuit, the master for transferring information to and from the DRAM via the bus, the master for signaling the beginning of an operation to the DRAM only on even cycles.

26. A dynamic random access memory (DRAM), comprising:

a first circuit for providing a plurality of phases of a clock signal;

a conductor for coupling the DRAM to a bus; and

a plurality of input receivers coupled to the conductor and the first circuit, wherein each input receiver is coupled to receive a corresponding one of the plurality of phases of the clock signal such that each input receiver latches information received from the conductor in response to a rising edge of the corresponding phase of the clock signal.

27. The DRAM of claim 26, wherein the first circuit provides the plurality of phases of the clock signal in response to an externally provided clock signal.

28. A dynamic random access memory (DRAM), comprising:

a first circuit for providing a plurality of phases of a clock signal;

a conductor for coupling the DRAM to a bus;

a multiplexer coupled to the first circuit, the multiplexer having an output and a plurality of inputs;

an output driver including an output coupled to the conductor and an input coupled to the output of the multiplexer, the output driver for driving data on the conductor in response to the output of the multiplexer; and

a plurality of output lines coupled to the plurality of inputs of the multiplexer, wherein each output line is coupled to the output of the multiplexer in response to the multiplexer detecting a rising edge of a phase of the clock signal that corresponds to that output line.

29. The DRAM of claim 28, wherein the first circuit provides the plurality of phases of the clock signal in response to an externally provided clock signal.