Fabrication process for compound semiconductor device

• US 5,514,605 A
• Filed: 08/17/1995
• Issued: 05/07/1996
• Est. Priority Date: 08/24/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Asai, Shuji, Kohno, Michihisa
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/516,292
• Time in Patent Office: 264 Days
• Field of Search: 437/40 LC, 437/40 SH, 437/41 LC, 437/41 SH, 437/133, 437/56, 437/912, 437/234
• US Class Current: 438/172
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors

Abstract

On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.

Claims

1. A fabrication process of a compound semiconductor device comprising:

a first step of sequentially growing a first conductive type semiconductor layer group, a second conductive semiconductor layer group and a low resistance conductive semiconductor layer on a semi-insulative semiconductor substrate in order;

a second step of forming a first insulation layer on said low resistance conductive semiconductor layer and forming first and second gate openings by selectively etching said first insulation layer;

a third step of selectively etching said low resistance conductive semiconductor layer exposed by said first and second gate openings formed in said first insulation layer to expose the surface of said second conductive semiconductor layer group to form third and fourth gate openings continuous to said first and second gate openings;

a fourth step of forming a side wall insulation layer in a side wall of said first to fourth gate openings by depositing second insulation layer on entire surface and by etching back said second insulation layer;

a fifth step of selectively etching said second conductive semiconductor layer group exposed through said third gate opening with masking the second and fourth gate openings to expose the surface of said first conductive semiconductor layer group to form a fifth gate opening continuous to said third gate opening; and

a sixth step of forming a first gate electrode contacting with the surface of said first conductive semiconductor layer group via said first, third and fifth gate openings and with a side surface of the second conductive semiconductor layer group, and a second gate electrode contacting with said second conductive semiconductor layer group via said second and fourth gate openings.

2. A fabrication process of a compound semiconductor device as set forth in claim 1, wherein said second conductive semiconductor layer group includes a threshold value voltage controlling layer in a thickness less than or equal to 15 as a lower layer, and an etching stop layer for stopping etching upon etching of said lower resistance conductive semiconductor layer as an upper layer, and

said fifth step includes a selective etching step for said etching stop layer and an isotropic dry etching step for said threshold voltage controlling layer.

3. A fabrication process of a compound semiconductor device as set forth in claim 2, wherein said second conductive semiconductor layer group includes a threshold value voltage controlling layer in a thickness less than or equal to 15 nm as a lower layer, and an etching stop layer for stopping etching upon etching of said lower resistance conductive semiconductor layer as an upper layer, and

said fifth step includes a selective etching step for said etching stop layer and an etching step for said threshold voltage controlling layer performed by generating a plasma by an electron cyclotron resonance.

4. A fabrication process of a compound semiconductor device as set forth in claim 2, wherein, said etching stop layer is an AlGaAs layer, and said threshold voltage controlling layer is an GaAs layer.

5. A fabrication process of a compound semiconductor device as set forth in claim 3, wherein, said etching stop layer is an AlGaAs layer, and said threshold voltage controlling layer is an GaAs layer.