Two-step sinter method utilized in conjunction with memory cell replacement by redundancies

• US 5,514,628 A
• Filed: 05/26/1995
• Issued: 05/07/1996
• Est. Priority Date: 05/26/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yoneoka, Yoshinobu, Ogata, Yoshihiro, Miyai, Yoichi, Enomoto, Osaomi
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/451,644
• Time in Patent Office: 347 Days
• Field of Search: 437/52, 437/8, 437/247, 437/923
• US Class Current: 438/6
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

A process is disclosed herein for increasing yield in a semiconductor circuity having redundant circuitry for replacing defective normal circuitry in the semiconductor integrated circuit. In the first step, an insufficient sinter operation (50) is carried out in a hydrogen atmosphere at a temperature of less than 350° C. At this temperature, no significant change will be seen in the interface trap density. Thereafter, the integrated circuit is tested (54,56) and the defective normal circuitry then is replaced (58) with the redundant circuitry. The integrated circuit is then subjected to a sufficient sinter operation (64) which is an operation wherein the substrate is disposed at a temperature between 350° C.-500° C. for more than 30 minutes. This sufficient sinter operation is performed in a hydrogen atmosphere, allowing dangling bonds at the interface to be terminated with hydrogen. Preferable, the optimal temperature for the sufficient sinter is approximately 400° C. The integrated circuit is then subjected to a reliability and burn-in procedure.

Claims

1. A process for increasing yield in a semiconductor integrated circuit having normal circuitry and redundant circuitry for replacing defective normal circuitry in the semiconductor circuit, the process comprising the steps of:

after formation of the circuitry on the integrated circuit, subjecting the integrated circuit to an insufficient sinter operation in an atmosphere having a hydrogen constituent that uses an operating environment that approximately maintains an interface trap density in the integrated circuit;

testing the integrated circuit to determine if any of the normal circuitry on the integrated circuit is defective;

replacing the defective normal circuitry on the integrated circuit with corresponding redundant circuitry; and

thereafter subjecting the integrated circuit to a sufficient sinter operation in an atmosphere having a hydrogen constituent that uses an operating environment that causes a decrease in the interface trap density in the integrated circuit.

2. To the process of claim 1, wherein the insufficient sinter operation is carried out at a temperature that is less than 350°

C.

3. The process of claim 2, wherein the sufficient sinter operation is carried out at a temperature in the range of 350°

C.-500°

C.

4. The process of claim 3, wherein the sufficient sinter operation is carried out at substantially 400°

C.

5. The process of claim 1, wherein the integrated circuit comprises a dynamic random access memory.

6. The process of claim 1, wherein the insufficient sinter operation is carried out at a temperature that will not cause a substantial decrease in the interface trap density in the integrated circuit.

7. The process of claim 1, wherein the sufficient sinter operation is carried out at a temperature that is at a level that will cause a substantial decrease in the interface trap density.