Multi-dimensional array video processor system

• US 5,515,076 A
• Filed: 03/22/1995
• Issued: 05/07/1996
• Est. Priority Date: 02/27/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Thompson, E. Earle, DeMond, Thomas W.
• Primary Examiner(s): BRIER, JEFFERY A
• Application Number:
  US08/408,765
• Time in Patent Office: 412 Days
• Field of Search: 345/139, 395/163, 395/164
• US Class Current: 345/505
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means
• CPC Class Codes: G02B 30/50 the image being built up from image elements distributed over a 3D volume, e.g. voxels
• CPC Class Codes: G02B 30/54 the 3D volume being generated by moving a 2D surface, e.g. by vibrating or rotating the 2D surface
• CPC Class Codes: G09F 19/18 involving the use of optical projection means, e.g. projection of images on clouds projection apparatus per se G03B
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: H04N 13/189 Recording image signals; Reproducing recorded image signals
• CPC Class Codes: H04N 13/194 Transmission of image signals
• CPC Class Codes: H04N 13/275 from 3D object models, e.g. computer-generated stereoscopic image signals
• CPC Class Codes: H04N 13/286 having separate monoscopic and stereoscopic modes
• CPC Class Codes: H04N 13/324 Colour aspects
• CPC Class Codes: H04N 13/363 using image projection screens volumetric display H04N13/388
• CPC Class Codes: H04N 13/365 using digital micromirror devices [DMD]
• CPC Class Codes: H04N 13/39 the picture elements emitting light at places where a pair of light beams intersect in a transparent material
• CPC Class Codes: H04N 13/393 the volume being generated by a moving, e.g. vibrating or rotating, surface
• CPC Class Codes: H04N 13/395 with depth sampling, i.e. the volume being constructed from a stack or sequence of 2D image planes
• CPC Class Codes: H04N 13/398 Synchronisation thereof; Control thereof
• CPC Class Codes: H04N 19/597 specially adapted for multi-view video sequence encoding
• CPC Class Codes: H04N 2005/7466 : Control circuits therefor
• CPC Class Codes: H04N 5/7458 : the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
• CPC Class Codes: H04N 9/3129 : scanning a light beam on the display screen scanning a light beam on a screen in displays other than projection devices G09G3/02; scanning systems in general G02B26/10; projectors using laser light sources in general H04N9/3161

Abstract

A digitized video system having a processor and a video memory. The processor converts a stream of digital information to extract planes of a three dimensional image to store into the video memory to display a three dimensional image. A spatial light modulator is connected to the video memory to receive and display a plane of said image to display a three dimensional image.

Claims

1. A video memory for storing a three dimensional image comprising:

(a) a plurality of regions of memory, each said region having a plurality of data units, each said data unit uniquely representing a single voxel of said image; and

(b) a bus interconnecting said regions for selectively receiving and transmitting said data units therebetween said regions; and

a plurality of controllers, wherein each said controller is uniquely connected to at least one of said regions and wherein each said controller is connected to said bus wherein said regions are interconnected through said controllers.

2. The video memory according to claim 1 wherein each said region represents a two dimensional slice of said image.

3. The video memory according to claim 1 wherein at least one of said controllers is a processor.

4. The video memory according to claim 1 wherein each data unit is comprised of a plurality of bits.

5. A processor system for generating and storing an image comprising:

(a) a memory having a plurality of regions, each said region having a plurality of data units, each said data unit uniquely representing a picture element of said image;

(b) a plurality of controllers, each said controller uniquely associated with at least one of said regions; and

(c) said controllers interconnected wherein a predetermined on of said data units in a predetermined one of said regions associated with a first of said controllers is selectively transmitted to a second of said controllers, wherein each said controller may selectively transmit an entire region.

6. The processor system according to claim 5 wherein each said data units comprise a plurality of bits.

7. The processor system according to claim 5 wherein said image is a three dimensional image.

8. The processor system according to claim 7 wherein each said region is a two dimensional slice of said three dimensional image.

9. The processor system according to claim 5 wherein said controllers are operative to modify said data units.

10. The processor system according to claim 5 wherein said controllers are operative to generate said data units.

11. The processor system according to claim 5 wherein said controllers are bit parallel processors

12. The processor system according to claim 5 including a bus wherein said controllers are interconnected by said bus.

13. The processor system according to claim 5 wherein said second controller is operative in response to said predetermined data unit to modify a second predetermined one of said data units.

14. The processor system according to claim 13 wherein said modification is replacement.

15. The processor system according to claim 5 including a host processor, said host processor coupled to each of said controllers.

16. The processor system according to claim 15 wherein said host processor is operative to selectively send commands to predetermined ones of said controllers.

17. The processor system according to claim 15 wherein said host processor is operative to simultaneously send commands to each of said controllers.

18. The processor system according to claim 15 wherein said host processor is coupled to said controllers via a bus.

19. The processor system according to claim 15 wherein predetermined ones of said controllers are operative to simultaneously operate on commands transmitted by said host to said predetermined ones of said controllers.

20. The processor system according to claim 19 wherein said predetermined ones of said controllers are all of said controllers.