Method for identifying excessive power consumption sites within a circuit

• US 5,515,302 A
• Filed: 11/07/1994
• Issued: 05/07/1996
• Est. Priority Date: 11/07/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Horr, Donald E., Maturo, Larry, Livingston, Kirk
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/334,987
• Time in Patent Office: 547 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 364/483, 395/750, 455/343, 331/1 A, 331/14-27, 324/537, 324/73.1, 257/148, 257/207, 257/208, 257/920, 326/56, 326/21, 371/25.1, 327/537, 327/546, 327/7, 365/210, 365/185, 365/230.03, 379/29, 379/18
• US Class Current: 358/1.15
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G06G 7/02 Details not covered by G06G7/04 - G06G7/10, e.g. monitoring, construction, maintenance

Abstract

A method for minimizing power consumption in a circuit is accomplished by identifying, based on the test parameters and topology information for the circuit, potential excessive power consuming sites. Next, the potential excessive power consuming sites, or potential leakage current sites, are monitored, based on the test parameters, for indeterminate logic states which result in leakage current and excessive power consumption. A report is generated detailing the locations of any leakage current sites, whereby the circuit may be modified to eliminate the leakage current sites prior to fabrication.

Claims

1. A method for identifying excessive power consumption sites within a circuit, the method comprising the steps of:

receiving test parameters for a logic simulation algorithm, wherein the logic simulation algorithm is used to test the circuit;

receiving circuit topology information of the circuit;

identifying a potential excessive power consuming site based on at least a portion of the circuit topology information;

while the logic simulation algorithm is testing the circuit, monitoring, based on at least a portion of the test parameters, the potential excessive power consuming site for an indeterminate logic state, the indeterminate logic state resulting in leakage current between any power supply conductor and any supply return conductor at the potential excessive power consuming site; and

when the indeterminate logic state is determined, identifying the potential excessive power consuming site as a site that is consuming excessive power due to the leakage current.

2. The method of claim 1, wherein the receiving test parameters step further comprises receiving input parameters and clock parameters as the test parameters.

3. The method of claim 2, wherein the receiving of clock parameters further comprises receiving a clock rate and a settling time.

4. The method of claim 3, wherein the monitoring the potential excessive power consuming site further comprises delaying the monitoring until the settling time has elapsed.

5. The method of claim 1 further comprises generating a report that details location of the potential excessive power consuming site.

6. The method of claim 1, wherein the identifying the potential excessive power consuming site as the site that is consuming excessive power further comprises identifying, for the potential excessive power consuming site, test parameters of the at least a portion of the test parameters causing the indeterminate logic state.

7. The method of claim 1, wherein the receiving circuit topology information further comprises receiving circuit topology information of an integrated circuit.

8. The method of claim 7, wherein the receiving circuit topology information further comprises receiving circuit topology information of a multi-layer integrated circuit.

9. A method for identifying excessive power consumption sites within a circuit, the method comprising the steps of:

receiving test parameters for a logic simulation algorithm, wherein the logic simulation algorithm is used to test the circuit;

receiving circuit topology information of the circuit;

identifying a potential excessive power consuming site based on at least a portion of the circuit topology information by searching the at least a portion of the circuit topology information for a transistor coupled to a gate of another transistor, for a transistor coupled to a power supply, or for a transistor coupled to a return;

while the logic simulation algorithm is testing the circuit, monitoring, based on at least a portion of the test parameters, the potential excessive power consuming site for an indeterminate logic state, the indeterminate logic state resulting in leakage current between the power supply and the return at the potential excessive power consuming site; and

when the indeterminate logic state is determined, identifying the potential excessive power consuming site as a site that is consuming excessive power due to the leakage current.

10. A method for producing an integrated circuit, the method comprising the steps of:

a) receiving test parameters for a logic simulation algorithm, wherein the logic simulation algorithm is used to test the integrated circuit;

b) receiving integrated circuit topology information of the integrated circuit;

c) identifying a potential excessive power consuming site based on at least a portion of the integrated circuit topology information;

d) while the logic simulation algorithm is testing the integrated circuit, monitoring, based on at least a portion of the test parameters, the potential excessive power consuming site for an indeterminate logic state;

e) when the indeterminate logic state is determined, identifying the potential excessive power consuming site as a site that is consuming excessive power due to leakage current resulting from the indeterminate logic state;

f) when the indeterminate logic state is determined, modifying the integrated circuit to eliminate the indeterminate logic state to produce a modified integrated circuit topology; and

g) fabricating the integrated circuit using the modified integrated circuit topology.

11. A method for testing a multi-layer integrated circuit, the method comprising the steps of:

a) receiving test parameters for a logic simulation algorithm, wherein the logic simulation algorithm is used to test the multi-layer integrated circuit;

b) receiving multi-layer integrated circuit topology information of the multi-layer integrated circuit;

c) identifying a potential excessive power consuming site based on at least a portion of the multi-layer integrated circuit topology information;

d) while the logic simulation algorithm is testing the multi-layer integrated circuit, monitoring, based on at least a portion of the test parameters, the potential excessive power consuming site for an indeterminate logic state that results in leakage current;

e) when the indeterminate logic state is determined, identifying the potential excessive power consuming site as a site that is consuming excessive power due to the leakage current; and

f) when the indeterminate logic state is determined, modifying the multi-layer integrated circuit to eliminate the indeterminate logic state to produce a modified multi-layer integrated circuit topology.