Semiconductor memory device

• US 5,515,312 A
• Filed: 10/13/1994
• Issued: 05/07/1996
• Est. Priority Date: 02/15/1994
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sumi, Tatsumi, Nakakuma, Tetsuji, Mukunoki, Toshio, Hirano, Hiroshige, Nakane, George, Moriwaki, Nobuyuki
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/322,541
• Time in Patent Office: 572 Days
• Field of Search: 365/117, 365/145, 365/201, 365/189.01
• US Class Current: 365/145
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

Claims

1. A semiconductor memory device comprising:

a pair of bit lines;

a word line;

a cell plate electrode;

a memory cell for storing normal data, connected to said bit lines, said word line, and said cell plate electrode; and

a prevention means for preventing readout of said normal data stored in said memory cell by destroying said normal data, after a number of readouts already executed on said normal data reaches a predetermined limiting number of readouts.

2. A semiconductor memory device according to claim 1, wherein said memory cell comprises a MOS transistor and a ferroelectric capacitor.

3. A semiconductor memory device comprising:

a pair of bit lines;

a word line;

a cell plate electrode;

a memory cell for storing data, connected to said bit lines, said word line, and said cell plate electrode; and

a prevention means for preventing normal readout of said data store in said memory cell, after a number of readouts already executed on said data reaches a predetermined limiting number of readouts, wherein said preventing means comprises an alteration means for altering bit line capacitance of at least one of said bit lines.

4. A semiconductor memory device according to claim 3, wherein said alteration means comprises a switch connected to a capacitor, wherein said switch is also connected to at least one of said bit lines for preventing readouts on said one or more connected bit lines.

5. A semiconductor memory device according to claim 4, wherein bit line capacitances of a first of said bit lines is different from bit line capacitance of a second of said bit lines when said switch is on.

6. A semiconductor memory device according to claim 4, further comprising at least one adjusting capacitor connected to at least one of said bit lines for adjusting bit line capacitance of said one or more connected bit lines, wherein said bit lines have approximately equal capacitance when said switch is on.

7. A semiconductor memory device according to claim 4, wherein bit line capacitance of said bit lines when said switch is on differs from bit line capacitance of said bit lines when said switch is off.

8. A semiconductor memory device according to claim 3, further comprising a control means connected to said alteration means for determining whether a number of readouts already executed on said stored data has reached said predetermined limiting number of readouts.

9. A semiconductor memory device according to claim 8, wherein said control means comprises a subtraction circuit for subtracting a number of readouts already executed on said stored data from said predetermined limiting number of readouts, a memory means for memorizing said subtracted number, and a judging circuit for determining whether said subtracted number has reached said predetermined limiting number of readouts.

10. A semiconductor memory device comprising:

a pair of bit lines;

a word line;

a cell plate electrode;

a memory cell for storing data, connected to said bit lines, said word line, and said cell plate electrode; and

a prevention means for preventing normal readout of said data stored in said memory cell, after a number of readouts already executed on said data reaches a predetermined limiting number of readouts, wherein said prevention means comprises a signal reversing means for altering a normal reversing timing for a rewriting operation of at least one logical voltage supplied to said memory cell for a rewriting operation conducted after said predetermined limiting number of readouts have been executed.

11. A semiconductor memory device according to claim 10, wherein said signal reversing means comprises an equalizing means for equalizing logical voltages of said bit lines after said predetermined limiting number of readouts have been executed on said stored data.

12. A semiconductor memory device according to claim 11 wherein said equalizing means comprises a reversing means for reversing logical voltage of one of said bit lines by a control signal precharging said bit lines.

13. A semiconductor memory device according to claim 11, further comprising a pair of data lines, each respectively connected to one of said bit lines, wherein said equalizing means comprises said data lines, supplying equal logical voltages to both of said bit lines.

14. A semiconductor memory device according to claim 10, wherein said signal reversing means comprises a voltage reversing means for reversing logical voltages of said bit lines and subsequently reversing logical voltage of said cell plate electrode.

15. A semiconductor memory device according to claim 10, further comprising a control means connected to said signal reversing means, wherein said control means determines whether a number of readouts already executed on said stored data has reached said predetermined limiting number of readouts.

16. A semiconductor memory device according to claim 15, wherein said control means comprises a subtraction circuit for subtracting a number of readouts already executed on said stored data from said predetermined limiting number of readouts, a memory means for memorizing said subtracted number, and a judging circuit for determining whether said subtracted number has reached said predetermined limiting number of readouts.

17. A semiconductor memory device comprising:

a pair of bit lines;

a word line;

a cell plate electrode;

a memory cell for storing data, connected to said bit lines, said word line, and said cell plate electrode; and

a prevention meads for preventing normal readout of said data stored in said memory cell, after a number of readouts already executed on said data reaches a predetermined limiting number of readouts, wherein said prevention means is a stopping means for stopping supply of a control signal to said memory cell after said predetermined limiting number of readouts have been executed on said stored data.

18. A semiconductor memory device according to claim 17, further comprising:

a sense amplifier connected to said bit lines, wherein said stopping means comprises a switch connected to said cell plate electrode and to said sense amplifier; and

a grounding means for grounding each of said cell plate electrode and said sense amplifier through said switch.

19. A semiconductor memory device according to claim 17, wherein said stopping means comprises a switch connected to said word line and to said cell plate electrode, and a grounding means for grounding said word line and said cell plate electrode through said switch.

20. A semiconductor memory device according to claim 17, further comprising a control means connected to said stopping means, wherein said control means determines whether a number of readouts already executed on said stored data has reached said predetermined limiting number of readouts.

21. A semiconductor memory device according to claim 20, wherein said control means comprises a subtraction circuit for subtracting a number of readouts already executed on said stored data from said predetermined limiting number of readouts, a memory means for memorizing said subtracted number, and a judging circuit for determining whether said subtracted number has reached said predetermined limiting number of readouts.

22. A method of limiting a number of readouts of normal data stored in a semiconductor memory device comprised of a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to said bit lines, said word line, and said cell plate electrode, wherein said limiting method comprises the steps of:

determining a number of readouts already executed on said normal data;

determining whether said number of readouts already executed on said normal data has reached a predetermined limiting number of readouts;

preventing subsequent readouts of said normal data by destroying said normal data upon determination that said number of readouts already executed on said normal data has reached said predetermined limiting number of readouts.

23. A method according to claim 22, wherein said memory cell is comprised of a MOS transistor and a ferroelectric capacitor.

24. A method according to claim 22, wherein said step of determining whether said number of readouts already executed on said normal data has reached said predetermined limiting number of readouts is achieved by a control means.

25. A method of limiting a number or readouts of data stored in a semiconductor memory device comprised of a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to said bit lines, said word line, and said cell plate electrode, wherein said limiting method comprises the steps of:

determine a number of readouts already executed on said stored data;

determining whether said number of readouts already executed on said stored data has reached a predetermined limiting number of readouts;

preventing subsequent readouts of said stored data upon determination that said number of readouts already executed on said stored data has reached said predetermined limiting number of readouts,

wherein said step of determining whether said number of readouts already executed on said stored data has reached said predetermined limiting number of readouts is achieved by a control means comprising;

a subtracted circuit for subtracting a number of readouts already executed on said stored data from said predetermined limiting number of readouts;

a memory means for memorizing said subtracted number; and

a judging circuit for determine whether said subtracted number has reached said predetermined limiting number of readouts.

26. A method of limiting a number of readouts of data stored in a semiconductor memory device comprised of a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to said bit lines, said word line, and said cell plate electrode, wherein said limiting method comprises the steps of:

determining a number of readouts already executed on said stored data;

determining whether said number of readouts already executed on said stored data has reached a predetermined limiting number of readouts;

preventing subsequent readouts of said stored data upon determination that said number of readouts already executed on said stored data has reached said predetermined limiting number of readouts, by altering bit line capacitance of at least one of said bit lines.

27. A method according to claim 26, wherein said semiconductor memory device further comprises at least one adjusting capacitor connected by a switch to at least of one of said bit lines, and said preventing step is achieved by adjusting said bit line capacitance of at least one of said bit lines by turning on said switch, connecting said adjusting capacitor to said connected bit line.

28. A method of limiting a number of readouts of data stored in a semiconductor memory device comprised of a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to said bit lines, said word line, and said cell plate electrode, wherein said limiting method comprises the steps of:

determining a number of readouts already executed on said stored data;

determining whether said number of readouts already executed on said stored data has reached a predetermined limiting number of readouts;

preventing subsequent readouts of said stored data upon determination that said number of readouts already executed on said stored data has reached said predetermined limiting number of readouts, by equalizing logical voltage of said bit lines.