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Addressing modes for a dynamic single bit per cell to multiple bit per cell memory

  • US 5,515,317 A
  • Filed: 06/02/1994
  • Issued: 05/07/1996
  • Est. Priority Date: 06/02/1994
  • Status: Expired due to Term
First Claim
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1. A memory system comprising:

  • a plurality of memory cells for storing one of a plurality of threshold levels in said memory cells, wherein said threshold levels demarcate 2n number of windows for designating states to represent storage of "n" bits of data for said memory cells; and

    an address buffer coupled to said memory cells for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" number of said memory cells, wherein said memory system exhibits a n;

    1 correspondence between memory locations and said physical addresses, and for generating at least one multi-level cell (MLC) address to identify a portion of said "n" bits of data within said "j" memory cells identified by each physical address.

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