Addressing modes for a dynamic single bit per cell to multiple bit per cell memory

• US 5,515,317 A
• Filed: 06/02/1994
• Issued: 05/07/1996
• Est. Priority Date: 06/02/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E., Robinson, Kurt B.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/252,920
• Time in Patent Office: 705 Days
• Field of Search: 365/184, 365/185, 365/182, 365/230.03, 365/230.08, 365/900, 365/230.01, 395/400
• US Class Current: 711/100
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory locations and the physical addresses when operating in the standard cell mode.

Claims

1. A memory system comprising:

a plurality of memory cells for storing one of a plurality of threshold levels in said memory cells, wherein said threshold levels demarcate 2ⁿ number of windows for designating states to represent storage of "n" bits of data for said memory cells; and

an address buffer coupled to said memory cells for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" number of said memory cells, wherein said memory system exhibits a n;

1 correspondence between memory locations and said physical addresses, and for generating at least one multi-level cell (MLC) address to identify a portion of said "n" bits of data within said "j" memory cells identified by each physical address.

2. The memory system as set forth in claim 1, further comprising:

a program controller including a command interface for receiving commands to operate said memory system; and

a multi-level cell (MLC) address register coupled to said program controller for receiving said MLC address via a command.

3. The memory system as set forth in claim 1, further comprising at least one input pin for receiving said MLC address.

4. The memory system as set forth in claim 1, wherein said physical address comprises:

a block address for identifying "i" blocks;

a row address for identifying "k" rows; and

a column address for identifying "m" columns.

5. The memory system as set forth in claim 1, wherein said "j" number of said memory cells for each physical address comprises 16, such that a word of 16 bits are identified for each physical address when operating in the standard cell mode, and (n*16) bits are identified for each physical address when operating in the MLC mode.

6. The memory system as set forth in claim 5, wherein said physical address comprises a byte address for selecting a high byte or low byte within said 16 bits identified for each physical address.

7. The memory system as set forth in claim 1, wherein said memory cells comprise flash electrically erasable programmable read only memory (EEPROM) cells.

8. The memory system as set forth in claim 1, further comprising:

a program controller including a command interface for receiving commands to operate said memory system;

a multi-level cell (MLC) address register coupled to said program controller for receiving said MLC address via a command for write operations; and

an input pin for receiving said MLC address for read operations.

9. The memory system as set forth in claim 8, wherein said address buffer generates a plurality of physical addresses to uniquely identify "j" contiguous memory cells, wherein said memory system maintains address coherency between operation in said MLC mode and said standard cell mode.

10. The memory system as set forth in claim 1, further comprising:

a switch control for permitting selection of an operating mode for said memory system including at least one multi-level cell (MLC) mode and a standard cell mode, wherein said MLC mode specifies storing more than a single bit of data for each memory cell and said standard cell mode specifies storing a single bit of data for each memory cell; and

a select circuit coupled to said switch control and said memory cells for reading a single bit per cell when said switch control indicates selection of said standard cell mode, and for reading multiple bits of data per memory cell when said switch control indicates selection of said multi-level cell mode, wherein said memory system maintains address coherency by exhibiting a n;

1 correspondence between memory locations and said physical addresses when operating in the MLC mode, and by exhibiting a 1;

1 correspondence between memory locations and said physical addresses when operating in the standard cell mode.

11. The memory system as set forth in claim 10, further comprising a program controller coupled to said switch control for programming control structure data in said standard cell mode, and for programming data structures in said MLC mode.

12. The memory system as set forth in claim 1, wherein said threshold levels demarcate four windows for designating four states to represent storage of two bits per memory cell.

13. The memory system as set forth in claim 12, wherein said MLC address comprises a single bit to identify "j/2" number of said memory cells.

14. A method for data storage, said method comprising the steps of:

storing one of a plurality of threshold levels in a plurality of memory cells, wherein said threshold levels demarcate 2ⁿ number of windows for designating states to represent storage of "n" bits of data for said memory cells;

generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" number of said memory cells, wherein said memory system exhibits a n;

1 correspondence between memory locations and said physical addresses; and

generating at least one multi-level cell (MLC) address to identify a portion of said "n" bits of data within said "j" memory cells identified by each physical address.

15. The method as set forth in claim 14, further comprising:

receiving commands via a command interface to operate said memory system; and

receiving said MLC address via a command in a multi-level cell (MLC) address register.

16. The method as set forth in claim 14, further comprising the step of receiving said MLC address via an input pin.

17. The method as set forth in claim 14, further comprising the steps of:

receiving commands via a command interface to operate said memory system;

receiving said MLC address via a command in a multi-level cell (MLC) address register for a write operation; and

receiving said MLC address via an input pin for a read operation.

18. The method as set forth in claim 14, wherein said threshold levels demarcate four windows for designating four states to represent storage of two bits per memory cell.

19. The method as set forth in claim 14, wherein said MLC address comprises a single bit to identify "j/2" number of said memory cells.

20. The method as set forth in claim 19, wherein the step of generating a plurality of physical addresses comprises the step of:

generating a block address for identifying "i" blocks;

generating a row address for identifying "k" rows; and

generating a column address for identifying "m" columns.

21. The method as set forth in claim 14, further comprising the steps of:

selecting an operating mode for said memory system including at least one multi-level cell (MLC) mode and a standard cell mode, wherein said MLC mode specifies storing more than a single bit of data for each memory cell and said standard cell mode specifies storing a single bit of data for each memory cell;

generating physical addresses for accessing a single bit per cell when operating in said standard cell mode to exhibit a 1;

1 correspondence between memory locations and said physical addresses; and

generating physical addresses including said MLC address for accessing multiple bits of data per memory cell when operating in said multi-level cell mode to exhibit a n;

1 correspondence between memory locations and said physical addresses.

22. The method as set forth in claim 21, further comprising the steps of:

programming control structure data in said standard cell mode; and

programming data structures in said MLC mode.

23. The method as set forth in claim 21, wherein:

the step of generating physical addresses for accessing a single bit per cell when operating in said standard cell mode comprises the step of generating physical addresses for accessing "j" contiguous memory cells; and

the step of generating physical addresses for accessing multiple bits of data per memory cell when operating in said multi-level cell mode comprises the step of generating physical addresses for accessing "j" contiguous memory cells, wherein address coherency is maintained between operation in said MLC mode and said standard cell mode.

24. The method as set forth in claim 14, wherein said memory cells comprise flash electrically erasable programmable read only memory (EEPROM) cells.

25. The method as set forth in claim 14, wherein said "j" number of said memory cells for each physical address comprises 16, such that a word of 16 bits are identified for each physical address when operating in the standard cell mode, and (n*16) bits are identified for each physical address when operating in the MLC mode.

26. The method as set forth in claim 25, wherein the step of generating a plurality of physical addresses comprises the step of generating a byte address for selecting a high byte or low byte within said 16 bits identified for each physical address.