Process for testing the operation of an application specific integrated circuit and application specific integrated circuit relating thereto

• US 5,515,382 A
• Filed: 07/06/1993
• Issued: 05/07/1996
• Est. Priority Date: 07/08/1992
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Lassorie, Jean-Louis
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Wachsman, Hal D.
• Application Number:
  US08/087,925
• Time in Patent Office: 1,036 Days
• Field of Search: 371/22.1, 371/22.3, 371/19, 371/25.1, 326/47, 326/61, 326/63, 326/101, 327/373, 327/564, 327/565, 364/490, 364/491
• US Class Current: 714/730
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

An application specific integrated circuit that comprises a central processing unit and a plurality of devices which are dependent on the application of the integrated circuit and are connected to the central processing unit. At least one shift register is provided by connecting in series elementary cells each mounted on a respective line corresponding to an input/output line of the central processing unit, each cell being able to inject into its respective line a value entered serially through the shift register, and further being able to sample the value of the binary signal carried by its respective line with a view to a reading of this value through the shift register. A method is provided for using the shift register to test the makeup of the application specific integrated circuit, or an application program executing on the central processing unit.

Claims

1. A process for testing the operation of an application specific integrated circuit formed on a single silicon chip, the application specific integrated circuit including a standardized central processing unit and application-dependent devices which are dependent on the application of the integrated circuit, the standardized central processing unit having a plurality of input/output gateways that are coupled to the application-dependent devices for interfacing the standardized central processing unit with the application-dependent devices during operation of the application specific integrated circuit, the application specific integrated circuit further including at least one shift register formed by connecting in series a set of elementary cells each mounted on a respective line carrying a binary signal of the integrated circuit, each cell being able to inject onto its respective line a value entered serially through the shift register and being able to sample the value of the binary signal carried by its respective line with a view to a reading of this value of the binary signal through the at least one shift register, the process comprising the steps of:

A. mounting the elementary cells of the at least one shift register between the standardized central processing unit and the application-dependent devices on lines corresponding to the input/output gateways of the standardized central processing unit;

B. executing a test program on the standardized central processing unit in the application specific integrated circuit, the test program generating test results on at least some of the input/output gateways of the standardized central processing unit; and

C. reading the test results through the at least one shift register.

2. The process as claimed in claim 1 wherein step B includes:

entering through the at least one shift register characteristic data of the devices which are dependent on the application and are connected to the standardized central processing unit;

storing the characteristic data; and

executing in the standardized central processing unit a test program stored in a program memory of the application specific integrated circuit, the test program including at least one instruction for reading the characteristic data and one instruction for storing the test results.

3. The process as claimed in claim 2, wherein the step of executing the test program includes executing at least one instruction that exchanges data between the standardized central processing unit and the application-dependent devices.

4. The process as claimed in claim 2, wherein the characteristic data is stored in an internal memory of the standardized central processing unit.

5. The process as claimed in claim 2, wherein the at least one shift register comprises elementary cells respectively mounted on lines of a data bus and an instruction bus of the standardized central processing unit, and wherein the steps of entering and storing the characteristic data include the steps of:

controlling the elementary cells of the at least one shift register to inject, onto the data bus, the characteristic data and to inject onto the instruction bus an instruction for writing data present on the data bus at a location in a memory, and

executing the instruction present on the instruction bus so that the characteristic data is written into the memory.

6. The process as claimed in claim 5, wherein step C includes:

controlling the elementary cells of the at least one shift register to inject onto the instruction bus an instruction for reading the test results and for presenting these test results on the data bus,

executing the instruction present on the instruction data bus, and

controlling the elementary cells of the at least one shift register to sample the value present on the data bus and to read the sampled value through the at least one shift register.

7. The process as claimed in claim 1 for testing an application program stored in a program memory of the application specific integrated circuit, wherein steps B and C include the following steps:

D. entering through the at least one shift register a verification address,

E. storing the verification address;

F. executing the application program as far as the instruction stored in the verification address in the program memory; and

G. reading through the at least one shift register values present on at least some of the gateways of the standardized central processing unit.

8. The process as claimed in claim 7, wherein step F includes the step of interrupting the application program when it reaches the instruction stored at the verification address in the program memory.

9. The process as claimed in claim 7, wherein the step of storing the verification address includes the step of storing the verification address in elementary cells of the at least one shift register which are mounted on lines of an instruction address bus of the standardized central processing unit.

10. The process as claimed in claim 9, wherein the elementary cells mounted on the lines of the instruction address bus include an output connected to the input of a comparator having another input connected to a program counter of the standardized central processing unit, step F further including the comparator activating a detection signal when the address supplied by the program counter is equal to the verification address.

11. The process as claimed in claim 9, wherein step A includes forming at least two data shift paths for the at least one shift register, a first data shift path being formed between elementary cells of a first group comprising elementary cells mounted respectively on lines of a data bus, a data address bus, an instruction bus, the instruction address bus, a command input bus and a command output bus of the standardized central processing unit, a second data shift path being formed between elementary cells of a second group comprising elementary cells mounted on lines of the instruction address bus of the standardized central processing unit, and

wherein the step of entering the verification address is performed serially through the second data shift path.

12. The process as claimed in claim 11, wherein the second data shift path furthermore includes elementary cells mounted on access lines of the standardized central processing unit serving to carry signals for selecting modes of execution of the procedure for testing the application program.

13. The process as claimed in claim 11, wherein the step of entering the verification address through the second data shift path is performed during an interrupt of the execution of the application program.

14. An application specific integrated circuit formed on a single silicon chip, comprising:

application-dependent devices which are dependent on the application of the integrated circuit;

a standardized central ;

processing unit having a plurality of input/output gateways that are coupled to the application-dependent devices for interfacing the standardized central processing unit with the application-dependent devices during operation of the application specific integrated circuit,

at least one shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to inject onto its respective line a value entered serially through the at least one shift register and being able to sample the value of the binary signal carried by its respective line with a view to a reading of this value through the at least one shift register; and

wherein the elementary cells of the at least one shift register are mounted between the standardized central processing unit and the application-dependent devices on lines corresponding to the input/output gateways of the standardized central processing unit.

15. The application specific integrated circuit as claimed in claim 14,

wherein the at least one shift register includes elementary cells mounted on lines of an instruction address bus of the standardized central processing unit in order to store a verification address which can be entered serially through the at least one shift register,

wherein the standardized central processing unit comprises a program counter in order to deliver on the instruction address bus addresses of locations of a program memory containing an application program, and

wherein the standardized central processing unit furthermore comprises a comparator having an input connected to the program counter and an input connected to the elementary cells mounted on the lines of the instruction address bus, the comparator being arranged to activate a detection signal when the address supplied by the program counter is equal to the verification address.

16. The application specific integrated circuit as claimed in claim 15, wherein the comparator is furthermore arranged to activate an interrupt signal delayed with respect to the detection signal in order to interrupt execution of the application program when it reaches the instruction stored at the verification address in the program memory.

17. The application specific integrated circuit as claimed in claim 15, wherein the at least one shift register includes at least two data shift paths, a first data shift path being formed between elementary cells of a first group comprising elementary cells mounted respectively on lines of a data bus, a data address bus, an instruction bus, the instruction address bus, a command input bus and a command output bus of the standardized central processing unit, a second data shift path being formed between elementary cells of a second group comprising elementary cells mounted on lines of the instruction address bus of the standardized central processing unit.

18. A process for testing the operation of an application specific integrated circuit formed on a single silicon chip, the application specific integrated circuit including a standardized processor and at least one application-dependent circuit, the standardized processor having a plurality of input/output lines for interfacing with the at least one application-dependent circuit, the process including the steps of:

A. forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements mounted between the standardized processor and the at least one application-dependent circuit, the serial scan path further including a respective scan path element mounted on each of the plurality of input/output lines for interfacing the standardized processor with the at least one application-dependent circuit;

B. executing a test program on the standardized processor in the application specific integrated circuit, the test program generating test results on at least some of the input/output lines of the standardized processor; and

C. reading the test results through the serial scan path.

19. The process as claimed in claim 18 wherein step B includes:

entering test data through the serial scan chain, the test data being characteristic of the at least one application-dependent circuit;

storing the test data within the application specific integrated circuit; and

executing a test program in the standardized processor that reads the test data, performs a processing operation on at least a portion of the test data, and stores test results of the processing operation.

20. The process as claimed in claim 19, wherein the step of executing the test program includes exchanging data between the standardized processor and the at least one application-dependent circuit.

21. The process as claimed in claim 19 wherein the standardized processor includes an internal memory, and wherein the test data and the test results are stored in the internal memory.

22. The process as claimed in claim 19 wherein the serial scan path includes scan path elements respectively mounted on lines of a data bus and an instruction bus of the standardized processor, wherein the standardized processor includes a memory, and wherein the steps of entering and storing test data include the steps of:

controlling the serial scan path to input test data that is characteristic of the at least one application-dependent circuit onto the data bus;

controlling the serial scan path to input onto the instruction bus an instruction for writing data present on the data bus at a location within the memory; and

executing the instruction present on the instruction bus so that the test data is written into the memory.

23. The process as claimed in claim 19, wherein the serial scan path includes scan path elements respectively mounted on lines of a data bus and an instruction bus of the standardized processor, wherein the standardized processor includes a memory, and the step of reading the stored test results includes the steps of:

controlling the serial scan path to input onto the instruction bus an instruction for reading the stored test results from the memory and for sourcing the test results to the data bus;

executing the instruction present on the instruction data bus so that the stored test results are read from the memory and sourced to the data bus; and

controlling the serial scan path so that the test results are stored from the data bus and serially read out of the application specific integrated circuit.

24. The process as claimed in claim 18 for testing an application program stored in a program memory within the application specific integrated circuit, wherein steps B and C include the steps of:

D. controlling the serial scan path to input a verification address;

E. storing the verification address within the application specific integrated circuit;

F. executing the application program until the address of the program memory matches the verification address; and

G. reading through the serial scan path at least some of the values present on the input/output lines interfacing the standardized processor with the at least one application-dependent circuit.

25. The process as claimed in claim 24, wherein step F includes the step of interrupting the application program when it reaches the instruction stored within the program memory at the verification address.

26. The process as claimed in claim 25 wherein the standardized processor includes a program counter and the application specific integrated circuit includes a comparator, the comparator having one input connected to the program counter of the standardized processor and the other input connected to a subset of the scan path elements, and wherein the storing of the verification address includes the step of storing the verification address within the subset of scan path elements;

and

wherein step F includes the step of activating a comparator output signal when the address supplied by the program counter is equal to the verification address.

27. The process as claimed in claim 18, wherein the step of forming a serial scan path includes forming first and second serial scan paths, each scan path including a plurality of scan path elements, the first serial scan path including a first group of scan path elements mounted respectively on lines of a data bus, a data address bus, an instruction bus, an instruction address bus, a command input bus and a command output bus of the standardized processor, the second serial scan path including a second group of scan path elements mounted respectively on lines of the instruction address bus of the standardized processor, and

wherein the step of entering the verification address is performed serially through the second serial scan path.

28. The process as claimed in claim 27 wherein the step of entering the verification address through the second serial scan path is performed during an interrupt of the execution of the application program.

29. An application specific integrated circuit formed on a single silicon chip, comprising:

a standardized processor;

at least one application-dependent circuit which is dependent on the application of the integrated circuit and which is connected to the standardized processor, the standardized processor having a plurality of input/output lines for interfacing with the at least one application-dependent circuit; and

at least one serial shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to output onto its respective line a value entered serially through the at least one serial shift register, each cell further being able to sample the value of a binary signal carried by its respective line so that binary signals on the lines on which the set of elementary cells is mounted can be read through the at least one serial shift register; and

wherein elementary cells of the at least one serial shift register are mounted between the standardized processor and the at least one application-dependent circuit on the input/output lines of the standardized processor that interface with the at least one application-dependent circuit.

30. An application specific integrated circuit as claimed in claim 29, wherein the application specific integrated circuit includes a program memory for storing an application program, wherein the at least one serial shift register includes a group of elementary cells mounted to store a verification address which can be entered serially through the at least one serial shift register, and wherein the application specific integrated circuit further includes:

a program counter in order to deliver on the instruction address bus addresses of the program memory locations including the application program; and

a comparator having a first input connected to the program counter and a second input connected to the group of elementary cells storing the verification address, the comparator being arranged to activate a detection signal when the address supplied by the program counter is equal to the verification address.

31. The application specific integrated circuit as claimed in claim 30, wherein the comparator is furthermore arranged to activate an interrupt signal delayed with respect to the detection signal in order to interrupt execution of the application program when it reaches the instruction stored at the verification address in the program memory.

32. The application specific integrated circuit as claimed in claim 31, wherein the at least one serial shift register includes at least two data shift paths, a first data shift path being formed between elementary cells of a first group comprising elementary cells mounted respectively on lines of a data bus, a data address bus, an instruction bus, an instruction address bus, a command input bus and a command output bus of the standardized processor, a second data shift path being formed between elementary cells of a second group comprising elementary cells mounted on lines of the instruction address bus of the standardized processor.

33. A process for testing the operation of an application specific integrated circuit formed on a single silicon chip, the application specific integrated circuit including a processor and a plurality of application-dependent circuits, the application specific integrated circuit having a plurality of internal connection lines for interfacing between the application-dependent circuits and for further interfacing between the processor and the plurality of application-dependent circuits, the process including the steps of:

forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements, each scan path element being mounted on a respective connection line;

entering test data through the serial scan path, the test data being characteristic of at least one of the plurality of application-dependent circuits;

storing the test data within the application specific integrated circuit;

executing a test program on the processor in the application specific integrated circuit that reads the test data and performs a processing operation on at least a portion of the test data;

storing test results of the processing operation in the application specific integrated circuit; and

reading the stored test results from the application specific integrated circuit.

34. A process for testing the operation of an application specific integrated circuit as recited in claim 33 wherein the step of storing the test results includes storing the test results in at least one scan path element, and wherein the step of reading the stored test results includes controlling the serial scan path to serially read the test results out of the integrated circuit.

35. A process for testing the operation of an application specific integrated circuit, the application specific integrated circuit including a processor and a plurality of application-dependent circuits, the application specific integrated circuit having a plurality of internal connection lines for interfacing between the application-dependent circuits and for further interfacing between the processor and the plurality of application-dependent circuits, the application specific integrated circuit further including a program memory for storing an application program for execution by the processor, the process including the steps of:

forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements, each scan path element being mounted on a respective connection line;

controlling the serial scan chain to input a verification address;

storing the verification address within the application specific integrated circuit;

executing the application program until the address of the program memory equals the verification address; and

reading a value present on at least one connection line of the processor out of the application specific integrated circuit.

36. A process for testing the operation of an application specific integrated circuit as recited in claim 35 wherein the step of reading a value present on at least one of the connection lines of the processor includes the steps of:

storing the at least one input/output line value in a scan path element; and

controlling the serial scan chain to serially read the value stored in the scan path element out of the application specific integrated circuit.

37. A process for testing the operation of an application specific integrated circuit, the application specific integrated circuit including a processor and a plurality of application-dependent circuits, the application specific integrated circuit having a plurality of internal connection lines for interfacing between the application-dependent circuits and for further interfacing between the processor and the plurality of application-dependent circuits, the application specific integrated circuit further including a program memory for storing an application program for execution by the processor, the process including the steps of:

forming a serial scan path through at least a portion of the application specific integrated circuit, the serial scan path including a plurality of scan path elements, each scan path element being mounted on a respective connection line;

determining a program memory failure address at which the application program fails;

starting execution of the application program;

halting execution of the application program at the determined failure address;

entering expected data through the serial scan chain so that the plurality of connection lines interfacing the processor to the plurality of application-dependent circuits include values equaling those that would be expected if the application program were to execute without failure; and

re-starting execution of the application program.

38. An application specific integrated circuit formed on a single silicon chip, comprising:

a standardized processor having a plurality of input/output lines;

at least one application-dependent device which is dependent on the application of the integrated circuit and is connected to at least one of the input/output lines of the standardized processor; and

a standardized shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to inject onto its respective line a value entered serially through the standardized shift register and being able to sample the value of the binary signal carried by its respective line so that the value can be read through the standardized shift register;

wherein an elementary cell of the standardized shift register is mounted between the standardized processor and the at least one application-dependent device on each of the at least one input/output line of the standardized processor that is connected to the application-dependent device.

39. An application specific integrated circuit formed on a single silicon chip, comprising:

a standardized device having a plurality of input/output lines;

at least one application-dependent device which is dependent on the application of the integrated circuit and is connected to at least one of the input/output lines of the standardized device; and

a shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the application specific integrated circuit, each cell being able to inject onto its respective line a value entered serially through the shift register and being able to sample the value of the binary signal carried by its respective line so that the value can be read through the shift register;

wherein an elementary cell of the shift register is mounted between the standardized device and the at least one application-dependent device on each of the at least one input/output line of the standardized device that is connected to the application-dependent device.

40. The application specific integrated circuit recited in claim 39, wherein the shift register is standardized.