Data processor and method utilizing coded no-operation instructions

• US 5,515,519 A
• Filed: 03/07/1994
• Issued: 05/07/1996
• Est. Priority Date: 03/19/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Arakawa, Fumio, Yajima, Hiroshi, Yoshioka, Shinichi, Kashiwagi, Yugo
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/207,785
• Time in Patent Office: 792 Days
• Field of Search: 395/375, 395/400, 395/700, 364/DIG. 1 MS File, 364/DIG. 2 MS File
• US Class Current: 712/234
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/4486 Formation of subprogram jump address

Abstract

A compiler incorporates obtained information for controlling the data-processor hardware, such as the position of the branch destination of a branch instruction and the used states of registers into object codes (NOP instruction) including a no-operation instruction code to post it to the data processor. The data processor is so constituted as to effectively use the data-processor resource not practically used by the no-operation instruction code and reflect the hardware control information included in the object code on data processing.

Claims

1. A microcomputer for executing a program having a plurality of instructions including at least one no-operation instruction, comprising:

a decoder which decodes the instructions;

an execution unit which executes a predetermined operation in accordance with the result of the decoding by the decoder;

a program counter which stores the address of the instruction to be next executed; and

a branch address register which stores the address of a branch destination;

wherein the no-operation instruction has a field for storing data for the branch destination address of a branch instruction issued after the no-operation instruction,

the execution unit executes an operation corresponding to an address of the branch destination of the branch instruction using the data stored in the field of the no-operation instruction, and

the result of the operation executed by the execution unit is stored in the branch address register as the address of the branch destination of the branch instruction.

2. The microcomputer according to claim 1, further including:

an address register for storing an instruction address other than the branch destination address; and

a selector for supplying one of the branch destination address in the branch address register and the address in the address register to the program counter.

3. The microcomputer according to claim 2, further including:

a control unit including a flag set when a predetermined condition is met by executing a predetermined instruction among the instructions.

4. The microcomputer according to claim 3, wherein the branch address register has information for showing whether the branch destination address stored in the branch address register is valid.

5. The microcomputer according to claim 4, wherein the selector supplies the branch destination address stored in the branch address register to the program counter when the flag is set and the information shows that the branch destination address stored in the branch address register is valid.

6. A microcomputer for executing a program having a plurality of instructions including at least one no-operation instruction, comprising:

a decoder which decodes the instructions;

an execution unit which executes a predetermined operation in accordance with the result of the decoding by the decoder; and

a plurality of registers for storing predetermined data;

wherein

the no-operation instruction has a field for storing a number identifying a predetermined register available to store the return destination address of a subroutine, and

the return destination address of the subroutine is stored in the predetermined register as the result of decoding the field of the no-operation instruction by the decoder.

7. The microcomputer according to claim 6, further comprising:

a number specifying register coupled to the plurality of registers, wherein the number specifying register has an area for specifying the number of the predetermined register.

8. The microcomputer according to claim 7, wherein the number specifying register has a plurality of areas for specifying a plurality of predetermined registers.

9. The microcomputer according to claim 8, further comprising a control register having an area for showing the number of predetermined registers specified by the number specifying register.

10. The microcomputer according to claim 9, wherein the control register stores information for showing whether a register number stored in each area of the number specifying register is valid.

11. A microcomputer for executing a program having a plurality of instructions including at least one no-operation instruction, comprising:

a decoder which decodes the instructions;

an execution unit which executes a predetermined operation in accordance with the result of the decoding by the decoder;

a cache memory which stores the instructions; and

a cache control register having information for showing whether replacement of the instructions stored in the instruction cache memory is inhibited;

wherein the no-operation instruction has a field for storing information for showing whether the no-operation instruction is present in a loop, and

in response to decoding of the no-operation instruction by the decoder, information for inhibiting the replacement of the instructions stored in the cache memory is set in the cache control register in order to inhibit the replacement of the instructions if information showing that the no-operation instruction is present in the loop is stored in the field of the no-operation instruction.

12. In a computing apparatus, a method comprising the steps of:

generating an object program, wherein the object program comprises a plurality of instructions, wherein the plurality of instructions comprise at least one no-operation instruction comprising one or more fields, wherein the one or more fields of the no-operation instruction contain control information;

storing the object program in a memory;

retrieving the instructions of the object program from the memory;

decoding the instructions of the object program;

executing the instructions of the object program;

wherein, responsive to the decoding of the no-operation instruction, the execution of the instructions is responsive to the control information of the one or more fields of the no-operation instruction.

13. The method as claimed in claim 12, wherein the control information comprises branch destination information for a branch instruction of the object program.

14. The method as claimed in claim 12, wherein the control information comprises information identifying a register for storing the return address of a subroutine of the object program.

15. The method as claimed in claim 12, wherein the control information comprises information inhibiting replacement of instructions in a cache memory of the computing apparatus if the no-operation instruction is present in a loop of the object program.