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Data processor and method utilizing coded no-operation instructions

  • US 5,515,519 A
  • Filed: 03/07/1994
  • Issued: 05/07/1996
  • Est. Priority Date: 03/19/1993
  • Status: Expired due to Term
First Claim
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1. A microcomputer for executing a program having a plurality of instructions including at least one no-operation instruction, comprising:

  • a decoder which decodes the instructions;

    an execution unit which executes a predetermined operation in accordance with the result of the decoding by the decoder;

    a program counter which stores the address of the instruction to be next executed; and

    a branch address register which stores the address of a branch destination;

    wherein the no-operation instruction has a field for storing data for the branch destination address of a branch instruction issued after the no-operation instruction,the execution unit executes an operation corresponding to an address of the branch destination of the branch instruction using the data stored in the field of the no-operation instruction, andthe result of the operation executed by the execution unit is stored in the branch address register as the address of the branch destination of the branch instruction.

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