×

Method for forming LDD CMOS with oblique implantation

  • US 5,516,711 A
  • Filed: 12/16/1994
  • Issued: 05/14/1996
  • Est. Priority Date: 12/16/1994
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of forming a semiconductor integrated circuit comprising the steps of:

  • providing a semiconductor substrate having a first well region of a first conductivity type and a second well region of a second conductivity type;

    forming a first gate electrode overlying gate dielectric on said first well region and a second gate electrode overlying gate dielectric on said second well region;

    implanting first impurities at a first implant angle into said first well region and adjacent to said first gate electrode, and said second well region and adjacent to said second gate electrode, said first implant step being at said second conductivity type and at a first dose;

    forming sidewall spacers on edges of said first gate electrode and said second gate electrode;

    implanting second impurities at a second angle into said first well region and adjacent to said first gate electrode, said second implant being at said second conductivity type and at a second dose which is greater than said first dose;

    implanting third impurities at a third angle into said second well region and adjacent to said second gate electrode, said third implant step being at said first conductivity type and at a third dose; and

    implanting fourth impurities at a fourth angle into said second well region and adjacent to said second gate electrode, said fourth implant step being at said first conductivity type and at a fourth dose which is different from said third dose;

    wherein said fourth implant step forms an LDD (lightly doped drain) region in said second well region, said LDD region extending under a first portion of said sidewall spacers on said edges of said second gate electrode and extending under a portion of said second gate electrode, and said third implant step forming a S/D (source/drain) region in said second well region, said S/D region extending under a second portion of said sidewall spacers on said edges of said second gate electrode, the LDD region portion under said second gate electrode being of a greater length than the LDD region portion under said sidewall spacers.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×