High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance

• US 5,516,731 A
• Filed: 06/02/1994
• Issued: 05/14/1996
• Est. Priority Date: 06/02/1994
• Status: Expired due to Term

• Current Assignee: LSI Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Owens, Alexander H., Lyu, Michael, Toutounchi, Shahin, Yee, Abraham
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/252,723
• Time in Patent Office: 712 Days
• Field of Search: 437/247, 437/170, 437/171, 437/156, 437/76, 437/51, 437/938, 437/928, 437/57, 257/921, 257/547
• US Class Current: 438/13
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/326 Application of electric currents or fields, e.g. for electroforming H01L21/20 - H01L21/288 and H01L21/302 - H01L21/324 take precedence
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: Y10S 438/953 Making radiation resistant device

Abstract

A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.

Claims

1. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies comprising:

a) fabricating one or more CMOS integrated circuit dies;

b) forming over each of said integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

c) forming holes through said passivation layer to underlying portions of said CMOS integrated circuit dies; and

d) removing hydrogen from said CMOS integrated circuit dies by venting said hydrogen through said holes in said passivation layer.

2. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies comprising:

a) fabricating one or more CMOS integrated circuit dies;

b) forming over each of said integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

c) forming a plurality of holes through said passivation layer; and

d) applying an elevated temperature and an electrical bias to said CMOS integrated circuit dies for a period of time sufficient to permit hydrogen in said CMOS integrated circuit dies to be vented through said holes in said passivation layer.

3. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies comprising:

a) fabricating one or more CMOS integrated circuit dies;

b) forming over each of said CMOS integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

c) forming holes through said passivation layer; and

d) applying an elevated temperature to the integrated circuit dies for a period of time sufficient to permit hydrogen in said CMOS integrated circuit dies to be vented through said holes in said passivation layer.

4. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies, comprising:

a) fabricating one or more CMOS integrated circuit dies, each having a substrate;

b) forming over each of said CMOS integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

c) forming contact holes through said passivation layer;

d) forming metal contacts in said contact holes; and

e) applying an electrical bias to the integrated circuit dies for a period of time sufficient to permit hydrogen in said CMOS integrated circuit dies to be vented through the contact holes.

5. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies according to claim 4, further comprising:

applying an elevated temperature to the integrated circuit dies along with the electrical bias.

6. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies according to claim 5, wherein:

the electrical bias is applied to the integrated circuit dies by applying a first voltage to the metal contacts of each die and applying a voltage more positive than the first voltage to the substrate of each die.

7. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies according to claim 4, wherein:

the electrical bias is applied to the integrated circuit dies by applying a first voltage to the metal contacts of each die and applying a voltage more positive than the first voltage to the substrate of each die.

8. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies, comprising:

a) fabricating a plurality of CMOS integrated circuit dies, each die having a substrate;

b) forming over each of said integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

c) forming contact holes through said passivation layer, and metal contacts in said contact holes; and

d) repeating the steps of;

i) applying an elevated temperature to the CMOS integrated circuit dies to permit hydrogen in said CMOS integrated circuit dies to be vented through said holes in said passivation layer; and

ii) testing one or more of the CMOS integrated circuit dies for radiation hardness and hot electron resistance;

until radiation hardness and hot electron resistance is achieved.

9. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies according to claim 8, further comprising:

applying an electrical bias to the CMOS integrated circuit dies along with the elevated temperature.

10. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies according to claim 9, wherein:

the electrical bias is applied to the integrated circuit dies by applying a first voltage to the metal contacts of each die and applying a voltage higher than the first voltage to the substrate of each die.

11. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies, comprising:

a) fabricating a plurality of CMOS integrated circuit dies, each die having a substrate;

b) forming over each of said integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

c) forming contact holes through said passivation layer;

d) forming metal contacts in said contact holes; and

e) repeating the steps of;

i) applying an electrical bias to the CMOS integrated circuit dies to permit hydrogen in said CMOS integrated circuit dies to be vented through said holes in said passivation layer; and

ii) testing one or more of the CMOS integrated circuit dies for radiation hardness and hot electron resistance;

until radiation hardness and hot electron resistance is achieved.

12. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies according to claim 11, wherein:

the electrical bias is applied to the integrated circuit dies by applying a first voltage to the metal contacts of each die and applying a voltage higher than the first voltage to the substrate of each die.