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High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance

  • US 5,516,731 A
  • Filed: 06/02/1994
  • Issued: 05/14/1996
  • Est. Priority Date: 06/02/1994
  • Status: Expired due to Term
First Claim
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1. A method of making radiation hardened, hot-electron resistant CMOS integrated circuit dies comprising:

  • a) fabricating one or more CMOS integrated circuit dies;

    b) forming over each of said integrated circuit dies an overlying passivation layer selected from the group consisting of silicon nitride and silicon oxynitride;

    c) forming holes through said passivation layer to underlying portions of said CMOS integrated circuit dies; and

    d) removing hydrogen from said CMOS integrated circuit dies by venting said hydrogen through said holes in said passivation layer.

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