Nitride cap sidewell oxide protection from BOE etch

• US 5,517,045 A
• Filed: 11/04/1994
• Issued: 05/14/1996
• Est. Priority Date: 11/03/1993
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ho, Yen-Shyh, Chen, Chien-Yung
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US08/334,049
• Time in Patent Office: 557 Days
• Field of Search: 257/327, 257/338, 257/369
• US Class Current: 257/327
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: Y10S 438/911 Differential oxidation and etching
• CPC Class Codes: Y10S 438/918 Special or nonstandard dopant
• CPC Class Codes: Y10S 438/966 Selective oxidation of ion-amorphousized layer

Abstract

A new method of forming a self-aligned contact is achieved. A pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a TEOS layer over said silicon nitride layer is provided on a silicon substrate. Each of the layers has its side open to the ambient. Inert ions are implanted into the substrate which is not covered by the polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of the substrate. The pattern of polysilicon gate electrode stack and the surface of the said substrate are subjected to a thermal oxidizing ambient which causes oxidation of the sides open to the ambient of the polysilicon layer to form a second polyoxide layer on the sides of the polysilicon layer. A second silicon nitride layer is formed over the pattern of stack and the surface of the substrate. The second silicon nitride layer is anisotropically etched to remove the second silicon nitride from the top of the stack and from over the surface of the substrate while leaving the second silicon nitride layer remaining upon the sides of the stack to form a self-aligned opening to regions within the silicon substrate. A self-aligning contact to the regions is formed through said opening.

Claims

1. The self-aligned contact to regions within a silicon substrate comprising:

a pattern of polysilicon gate electrode stack on a silicon substrate including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a silicon oxide layer completely covering said silicon nitride layer;

a polyoxide layer on the sidewalls of said polysilicon gate electrode stack wherein said polyoxide layer has a convex shape on each of said sidewalls and does not contact said silicon substrate;

a second silicon nitride layer on the sidewalls of said polyoxide layer wherein said silicon nitride sidewalls have a more vertical shape than said polyoxide layer and wherein said silicon nitride sidewalls form a self-aligned opening to regions within said silicon substrate; and

a self-aligned contact to said regions through said opening.

2. The device of claim 1 wherein said silicon oxide layer overlying said silicon nitride layer is composed of tetraethoxysilane (TEOS) deposited to a thickness of between about 300 to 500 Angstroms and wherein said TEOS layer protects said underlying silicon nitride layer from damage during the etching process which forms said self-aligned opening.

3. The device of claim 1 wherein said polyoxide sidewalls have a thickness of between about 1850 to 2350 Angstroms.

4. The device of claim 1 wherein said second silicon nitride sidewall layer has a thickness of between about 550 to 650 Angstroms.

5. The integrated circuit device having a self-aligned contact to regions within a silicon substrate comprising:

a pattern of polysilicon gate electrode stack on a silicon substrate including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a silicon oxide layer over said silicon nitride layer;

a polyoxide layer on the sidewalls of said polysilicon gate electrode stack wherein said polyoxide layer has a convex shape on each of said sidewalls and does not contact silicon substrate;

a second silicon nitride layer on the sidewalls of said polyoxide layer wherein said silicon nitride sidewalls have a more vertical shape than said polyoxide layer and wherein said silicon nitride sidewalls form a self-aligned opening to regions within said silicon substrate;

a self-aligned contact to said regions through said opening; and

a metal layer filling said self-aligned contact opening.

6. The device of claim 5 wherein said silicon oxide layer overlying said silicon nitride layer is composed of tetraethoxysilane (TEOS) deposited to a thickness of between about 300 to 500 Angstroms and wherein said TEOS layer protects said underlying silicon nitride layer from damage during the etching process which forms said self-aligned opening.

7. The device of claim 5 wherein said polyoxide sidewalls have a thickness of between about 1850 to 2350 Angstroms.

8. The device of claim 5 wherein said second silicon nitride sidewall layer has a thickness of between about 550 to 650 Angstroms.