Semiconductor device for driving heat generator

• US 5,517,224 A
• Filed: 06/17/1993
• Issued: 05/14/1996
• Est. Priority Date: 06/18/1992
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Nakamura, Hiroyuki, Kaizu, Shunichi, Fujita, Kei, Kamei, Seiji, Ichise, Toshihiko
• Primary Examiner(s): Hartary, Joseph W.
• Application Number:
  US08/077,382
• Time in Patent Office: 1,062 Days
• Field of Search: 347/59, 347/58, 347/57, 347/209, 347/210, 257/336
• US Class Current: 347/59
• CPC Class Codes: B41J 2/1601 Production of bubble jet print heads B41J2/1606, B41J2/162 take precedence
• CPC Class Codes: B41J 2/1628 dry etching
• CPC Class Codes: B41J 2/1629 wet etching
• CPC Class Codes: B41J 2/1631 photolithography
• CPC Class Codes: B41J 2/1642 thin film formation by CVD [chemical vapor deposition]
• CPC Class Codes: B41J 2/1646 thin film formation by sputtering
• CPC Class Codes: B41J 2202/13 Heads having an integrated circuit
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

A semiconductor device has transistors, each transistor having a first conduction type of a first semiconductor region including a first main electrode region, a second conduction type of second semiconductor region including a channel region which is provided in the first semiconductor region, a second main electrode region provided in the second semiconductor region, a gate electrode on the channel region extending through a gate insulating film between the first and second main electrode regions. A portion of the first main electrode region which contacts the channel region is a high-resistance region. The semiconductor device also has buried-type element isolation regions which prevent the occurrence of latch up and bird'"'"'s beaks in the device.

Claims

1. A semiconductor device comprising:

a plurality of transistors, wherein each transistor comprises;

a first semiconductor region of a first conduction type, including a first main electrode region;

a second semiconductor region of a second conduction type, including a channel region, said second semiconductor region being disposed in said first semiconductor region and in contact therewith, said channel region being in contact with a portion of said first main electrode region;

a second main electrode region of the first conducting type disposed in said second semiconductor region and in contact with said channel region;

a gate insulating film disposed on said channel region;

a gate electrode disposed on said gate insulting film and in alignment with said channel region;

wherein

said portion of said first main electrode region which contacts said channel region is a high-resistance region.

2. A semiconductor device according to Claim 1, wherein said second main electrode region is connected to an electrothermal converter.

3. A semiconductor device according to claim 2, wherein a process of forming an electrode of said electrothermal converter comprises the first step of exposing to exposure energy a photoresist provided on a metal layer as a wiring electrode at a distance of 40 to 100 μ

m between said photoresist and a photomask disposed thereon and having a-wiring electrode pattern, and the second step of exposing to exposure energy said photoresist at a distance of 0 to 14 μ

m between said photoresist and said photomask.

4. A semiconductor device according to claim 3, wherein said process of forming an electrode of said electrothermal converter further comprises the development step of developing said photoresist after said second exposure step, and the etching step of etching said metal layer while contracting at least the end of said photoresist with an alkali solution during etching of said metal layer using said photoresist as a mask.

5. A semiconductor device according to claim 2, wherein said semiconductor device forms a thermal head.

6. A semiconductor device according to claim 2, wherein said semiconductor device forms an ink jet head.

7. A semiconductor device according to claim 1, wherein said transistors are provided in a matrix of dimensions N×

M and wherein said transistors are divided into groups corresponding to N, wherein a gate is common to the transistors in each group.

8. A semiconductor device according to claim 1, wherein said transistors are provided in a matrix of dimensions N×

M and wherein said transistors are divided into groups corresponding to N, wherein an electrothermal converter is connected to each of said transistors.

9. A semiconductor device according to claim 1, wherein said first main electrode region serves as a drain, and said second main electrode region serves as a source.

10. A semiconductor device according to claim 1, wherein said first semiconductor region comprises a buried layer, said high-resistance region disposed on said buried layer, and a low-resistance region adjacent to said high-resistance region.

11. A semiconductor device according to claim 1, wherein a plurality of said second main electrode regions are disposed in said second semiconductor region, and contact a common electrode.

12. A semiconductor device according to claim 4, wherein said second main electrode regions are connected to said second semiconductor region by said common electrode.

13. A semiconductor device according to claim 1, further comprising a plurality of element isolation regions arranged so that each of said transistors is electrically isolated.

14. A semiconductor device according to claim 13, wherein each of said element isolation regions has a first isolation region comprising a p-type semiconductor, and a second isolation region contained in said first isolation region comprising an n-type semiconductor, both isolation regions being in contact with a metal which forms a short circuit between said first and said second isolation regions.

15. A semiconductor device according to claim 13, wherein each of said element isolation regions comprises an insulating portion filled in a recessed portion.

16. A semiconductor device according to claim 15, wherein each of said element isolation regions is formed by a method of filling an insulator comprising a first step of coating the bottom and side of an opening with said insulator, and a second step of filling said opening with said insulator.

17. A semiconductor device according to claim 16, wherein the insulator filled in said first step is different from that filled in said second step.

18. A semiconductor device according to claim 17, wherein said insulator filled in said opening is levelled to the same height as that of the surface of said semiconductor substrate.

19. A semiconductor device according to claim 1, has a surface which is flattened.

20. An image forming apparatus comprising a semiconductor device, said semiconductor device comprising:

a plurality of transistors, wherein each transistor comprises;

a first semiconductor region of a first conducting type, including a first main electrode region;

a second semiconductor region of a second conduction type, including a channel region, said second semiconductor region being disposed in said first semiconductor region, and in contact therewith, said channel region being in contact with a portion of said first main electrode region;

a second main electrode region of the first conducting type disposed in said second semiconductor region and in contact with said channel region, and connected to an electrothermal converter;

a gate insulating film disposed on said channel region;

a gate electrode disposed on said gate insulating film and in alignment with said channel region;

said portion of said first main electrode region which contacts said channel region is a high-resistance region; and

wherein said semiconductor device forms a thermal head.

21. An image forming apparatus comprising a semiconductor device according to claim 20, further comprising said semiconductor device as a head for discharging ink by employing thermal energy.

22. An image forming apparatus according to claim 20, further comprising a conveyance means for conveying a medium.

23. An image forming apparatus according to claim 20, further comprising means for arranging said head opposite to said medium.