Multi-source video synchronization

• US 5,517,253 A
• Filed: 11/14/1994
• Issued: 05/14/1996
• Est. Priority Date: 03/29/1993
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: De Lange, Alphonsius A. J.
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): Burgess, Glenton B.
• Application Number:
  US08/335,805
• Time in Patent Office: 547 Days
• Field of Search: 348/513, 348/514, 348/511, 348/523, 348/571, 348/584, 348/714, 348/715, 348/512, 348/716, 345/119, 345/213
• US Class Current: 348/513
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A system for synchronizing input video signals from a plurality of video sources includes a plurality of buffering units (B1 . . . BN) each coupled to receive a respective one of the input video signals. The buffering units have mutually independent read and write operations. Each buffer write operation is locked to the corresponding video input signal. Each buffer read operation is locked to a system clock. The buffering units are substantially smaller than required to store a video signal field. The system further includes a storage arrangement (DRAM-1 . . . DRAM-M) for storing a composite signal composed from the input video signals, and a communication network (110) for communicating data from the buffering units to the storage arrangement, pixel (X) and line (Y) addresses of the buffering units and of the storage arrangement being coupled.

Claims

1. A system for synchronizing input video signals from a plurality of video sources, comprising:

means for buffering each respective one of said input video signals with mutually independent read and write operations, each write operation being locked to the corresponding video input signal, each read operation being locked to a system clock, said buffering means comprising a plurality of buffering units each corresponding to one of said video input signals and being substantially smaller than required to store a video signal field;

means for storing said input video signals to form a composite signal composed from said input video signals;

means for communicating data from said buffering units to said storage means; and

means for supplying common pixel and line count signals to pixel and line addresses of said buffering means and said storing means.

2. A synchronizing system as claimed in claim 1, wherein said storing means comprise a plurality (M) of storage units having mutually independent write controllers which are individually connectable to said buffering means.

3. A synchronizing system as claimed in claim 1, further comprising a buffer read control arrangement comprising for each buffering unit a counter for signalling whether the buffering unit is empty to disable buffer read out.

4. A synchronizing system as claimed in claim 3, wherein said storing means comprise a plurality (M) of storage units and said buffer read control arrangement is adapted to furnish data segments which are slightly larger than the number (L) of pixels per video line divided by the number (M) of storage units contained in said storage means.

5. A synchronizing system as claimed in claim 1, wherein said storage means comprise a circular memory having a capacity sufficient for one video field but too small to contain two video fields, and wherein a write address of said storage means is moved up by one field during a vertical blanking period when a read address of said storage means is about to pass said write address.

6. A synchronizing system as claimed in claim 1, wherein said storage means comprise a circular memory having a capacity sufficient for two video fields but too small to contain three video fields, and wherein a write address of said storage means is moved up by one frame during a vertical blanking period when a read address of said storage means is about to pass said write address.