Non-volatile semiconductor memory device capable of electrically performing read and write operation and method of reading information from the same

• US 5,517,445 A
• Filed: 10/30/1991
• Issued: 05/14/1996
• Est. Priority Date: 03/28/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Tosihba
• Original Assignee: Kabushiki Kaisha Tosihba
• Inventors: Abe, Kazuhide, Toyoda, Hiroshi, Yamakawa, Koji, Imai, Motomasa, Kohanawa, Yoshiko, Harata, Mitsuo
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/784,073
• Time in Patent Office: 1,658 Days
• Field of Search: 365/145, 365/149, 365/207, 365/208, 365/210
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A non-volatile semiconductor memory device, includes a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, the semiconductor layer and the ferroelectric layer forming a semiconductor-ferroelectric junction, a writing circuit in which a voltage higher than a coercive electric field of the ferroelectric material is applied to the capacitor of the memory cell to align a polarization direction of the ferroelectric layer in a predetermined direction so as to set a capacitance of the capacitor at a predetermined value, thereby writing data corresponding to the predetermined value of the capacitance, and a reading circuit in which a voltage less than the coercive electric field of the ferroelectric layer is applied to the capacitor of the memory cell in which the data is written, thereby reading the data.

Claims

1. A non-volatile semiconductor memory device, comprising:

a memory cell having a semiconductor-ferroelectric junction capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, said semiconductor layer and said ferroelectric layer forming a semiconductor-ferroelectric junction, the capacitance of said capacitor being changed a detectable amount based on the generation or disappearance of a depletion layer in said semiconductor layer adjacent to said semiconductor-ferroelectric junction;

writing means, in response to a voltage which is higher than a coercive electric field of said ferroelectric layer and is applied to said capacitor of said memory cell, for aligning a polarization direction of said ferroelectric layer in one of predetermined up and down directions with respect to a plane of the semiconductor-ferroelectric junction to set a capacitance of said capacitor at a predetermined value corresponding to the polarization direction based on the generation or disappearance of said depletion layer, and writing data corresponding to the predetermined value of said capacitance; and

reading means, in response to a voltage which is less than the coercive electric field of said ferroelectric layer and is applied to said capacitor of said memory cell in which the data is written, for reading the data, said data corresponding to a charge state of said capacitor;

wherein said writing means comprises;

a plate line connected to a first of said pair of electrodes of said capacitor;

a bit line connected through first switching means controlled by a word line to a second of said pair of electrodes of said capacitor;

wherein said voltage higher than said coercive electric field of said ferroelectric layer is applied by said bit line and said plate line;

and wherein said reading means comprises;

a select line controlling a second switching means thereby connecting a voltage lower than said coercive electric field to said second electrode of said capacitor;

wherein said capacitor is precharged via said voltage lower than said coercive electric field of said ferroelectric layer, the charge on said capacitor corresponding to the data of said memory cell.

2. The memory according to claim 1, wherein said ferroelectric layer has a Pb-based perovskite structure containing Pb(Zr_x Ti_l-x)O₃ as a major constituent.

3. The memory according to claim 1, wherein said capacitor includes:

a first insulating film formed on a semiconductor substrate;

a first electrode formed on said first insulating film;

said semiconductor layer formed on said first insulating film and contacting said first electrode;

said ferroelectric layer formed on said semiconductor layer and forming a Junction with said semiconductor layer; and

a second electrode formed on said ferroelectric layer.

4. The memory according to claim 1, wherein said capacitor includes:

a first insulating film formed on a semiconductor substrate;

a first electrode formed on said first insulating film;

said ferroelectric layer formed on said first electrode;

said semiconductor layer formed on said ferroelectric layer and forming a junction with said ferroelectric layer; and

a second electrode formed on said semiconductor layer.

5. A non-volatile semiconductor memory device, comprising:

a memory cell having a semiconductor-ferroelectric junction capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, said semiconductor layer and said ferroelectric layer forming a semiconductor-ferroelectric junction;

writing means, in response to a voltage which is higher than a coercive electric field of said ferroelectric layer and is applied to said capacitor of said memory cell, for aligning a polarization direction of said ferroelectric layer in one of predetermined up and down directions with respect to a plane of the semiconductor-ferroelectric junction to set a capacitance of said capacitor at a predetermined value corresponding to the polarization direction, and writing data corresponding to the predetermined value of said capacitance; and

reading means, in response to a voltage which is less than the coercive electric field of said ferroelectric layer and is applied to said capacitor of said memory cell in which the data is written, for reading the data, said data corresponding to a charge state of said capacitor;

wherein said capacitor includes;

a well region of a first conductivity type formed in a semiconductor substrate of the first conductivity type;

isolating means for electrically isolating said semiconductor substrate from said well region;

a first electrode contacting said well region;

said ferroelectric layer forming a semiconductor-ferroelectric junction with said well region; and

a second electrode contacting said ferroelectric layer.

6. The memory according to claim 5, wherein said isolating means is a semiconductor region of a second conductivity type formed between said semiconductor substrate and said well region, and said semiconductor substrate is isolated by a p-n junction from said well region.

7. A non-volatile semiconductor memory device, comprising:

a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between first and second electrodes to form a semiconductor-ferroelectric junction between said semiconductor layer and said ferroelectric layer, data being stored in said memory call by aligning a polarization direction of said ferroelectric layer in one of predetermined up and down directions with respect to a plane of the semiconductor-ferroelectric junction, wherein the capacitance of said capacitor is changed a detectable amount based on the generation or disappearance of a depletion layer in said semiconductor layer adjacent to said semiconductor-ferroelectric junction and a capacitance of said capacitor is set at a predetermined value corresponding to the polarization direction based on the generator or disappearance of said depletion layer;

a plate line, connected to said first electrode, for applying a first voltage to said first electrode;

a bit line for applying a second voltage to said second electrode, data stored in said memory being read out into said bit line during read access;

first switching means connected between said second electrode and said bit line;

a word line for supplying a first switching signal to said first switching means;

supply means for supplying a voltage higher than a coercive electric field of said ferroelectric layer to said second electrode during write access and supplying a voltage lower than a coercive electric field of said ferroelectric layer to said second electrode during read access;

second switching means connected between said second electrode and said supply means; and

a selection line for supplying a second switching signal to said second switching means.

8. Method for reading an information from a non-volatile semiconductor memory device, said memory device including:

a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between first and second electrodes to form a semiconductor-ferroelectric junction between said semiconductor layer and said ferroelectric layer, data being stored in said memory cell by aligning a polarization direction of said ferroelectric layer in one of predetermined up and down directions with respect to a plane of the semiconductor-ferroelectric junction, wherein the capacitance of said capacitor is changed a detectable amount based on the generation or disappearance of a depletion layer in said semiconductor layer adjacent to said semiconductor-ferroelectric junction and a capacitance of said capacitor is set at a predetermined value corresponding to the polarization direction;

a plate line, connected to said first electrode, for applying a first voltage to said first electrode;

a bit line for applying a second voltage to said second electrode, data stored in said memory being read out into said bit line during read access;

first switching means connected between said second electrode and said bit line;

a word line for supplying a first switching signal to said first switching means;

supply means for supplying a voltage higher than a coercive electric field of said ferroelectric layer to said second electrode during write access and supplying a voltage lower than a coercive electric field of said ferroelectric layer to said second electrode during read access;

second switching means connected between said second electrode and said supply means; and

a

selection line for supplying a second switching signal to said second switching means,

said method comprising the steps of;

setting a voltage of said bit line at a reference voltage;

turning said second switching means on to apply a voltage lower than said coercive electric field of said ferroelectric layer to said second electrode; and

turning said first switching means on to read out said data stored in said memory into said bit line.