Semiconductor memory device

• US 5,517,457 A
• Filed: 12/21/1994
• Issued: 05/14/1996
• Est. Priority Date: 12/21/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Masuoka, Fujio, Tanaka, Tomoharu, Nakamura, Hiroshi, Hasegawa, Takehiro, Momodomi, Masaki, Sakui, Koji
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/360,289
• Time in Patent Office: 510 Days
• Field of Search: 365/189.01, 365/189.04, 365/189.05, 365/230.01, 365/230.03, 365/230.04, 365/238, 365/238.5
• US Class Current: 365/230.03
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

Claims

1. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cell units arrayed in a matrix form, said memory cell unit having a plurality of memory cells connected;

word lines for selecting said memory cell;

bit lines for writing/reading data to/from said memory cell;

row selecting means for selecting said word line;

column selecting means for selecting said bit line; and

word line drivers, provided at both sides of said memory cell array, for driving a plurality of the word lines, wherein said word lines are divided into blocks each having a plurality of continually and adjacently provided word lines to be connected to said memory unit, and said word lines of the same block are connected to the corresponding same word line driver.

2. A semiconductor memory device according to claim 1, wherein said memory cell unit is formed by connecting said plurality of said memory cells in series, or connecting said plurality of said memory cells in parallel.

3. A semiconductor memory device according to claim 1, wherein each of said word blocks is alternately connected to word line drivers provided at both sides of said memory cell array every one block or every two blocks.

4. A semiconductor memory device according to claim 1, wherein the row selecting means is provided at both sides of said memory cell array to correspond to said word line driver.

5. A semiconductor memory device according to claim 4, further comprising a signal line for supplying an output signal sent from said row selecting means to said word line driver, wherein said signal line does not cross said memory cell array.

6. A semiconductor memory device according to claim 1, wherein only one of the driver circuits provided at the right and left of the memory cell array is selected to be operated during data erasing/writing.

7. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cell units formed on a semiconductor substrate in a matrix array, said memory cell unit having a plurality of electrically rewritable memory cells connected;

word lines for selecting said memory cell;

bit lines for writing/reading data to/from said memory cell;

row selecting means for selecting said word line;

column selecting means for selecting said bit line; and

word line drivers, provided at both sides of said memory cell array in a pitch of one to two memory cell units, for driving said word lines to correspond to every block of said memory unit as one block and to be connected said memory cell unit, wherein a plurality of the word lines provided to cross said memory cell unit of the same word line row are connected to the same driver.

8. A semiconductor memory device according to claim 7, wherein a row decoder is provided at both sides of said memory cell array to correspond to said word line driver.

9. A semiconductor memory device according to claim 7, further comprising a signal line for supplying an output signal sent from said row selecting means to said word line driver, wherein said signal line does not cross said memory cell array.

10. A semiconductor memory device according to claim 7, wherein said memory cell unit is formed by connecting said plurality of said memory cells in series, or connecting said plurality of said memory cells in parallel.

11. A semiconductor memory device according to claim 7, wherein only one of the driver circuits provided at the right and left of the memory cell array is selected to be operated during data erasing/writing.

12. A semiconductor memory device comprising:

a memory cell array wherein a memory cell unit having a plurality of electrically rewritable memory cells connected is formed, and said memory cell unit is formed on a semiconductor substrate in a matrix array;

a plurality of control gate lines provided to cross each memory cell unit of the same row;

bit lines each provided to cross said memory cell unit of the same column; and

word line drivers, provided at both sides of the memory cell array in a pitch of one to two memory cell units, for driving word lines wherein the plurality of the word lines provided to cross said memory cell unit of the even numbered row are connected to the driver provided at one end side of said memory cell array, and the plurality of the word lines provided to cross said memory cell unit of the odd numbered row are connected to the driver provided at the other end side of said memory cell array.

13. A semiconductor memory device according to claim 12, wherein the row selecting means is provided at both sides of said memory cell array to correspond to said word line driver.

14. A semiconductor memory device according to claim 12, further comprising a signal line for supplying an output signal sent from said row selecting means to said word line driver, wherein said signal line does not cross said memory cell array.

15. A semiconductor memory device according to claim 12, wherein said memory cell unit is formed by connecting said plurality of said memory cells in series, or connecting said plurality of said memory cells in parallel.

16. A semiconductor memory device according to claim 12, wherein only one of the driver circuits provided at the right and left of the memory cell array is selected to be operated during data erasing/writing.

17. A semiconductor memory device comprising:

a memory cell array wherein memory cell units provided in row and column directions in a matrix form, each memory cell unit having a plurality of memory cells of a MOSFET having a gate electrode, a source and drain, and an electrical charge storage layer;

a plurality of word lines connected to the gate electrode of said memory cell;

a plurality of bit lines connected to one of said source or drain located at one end of said units;

row selecting means provided in common to said memory cell units provided in the row direction, and coupled to said plurality of word lines;

column selecting means provided in common to said memory cell units provided in the column direction, and coupled to said plurality of bit lines; and

word line drivers, provided in an area, which is between said memory cell array and said row selecting means and which is the side of said two memory units provided in parallel in the column direction, and connected to drive said plurality of the word lines connected to only one of two memory cell units.

18. A semiconductor memory device according to claim 17, wherein said memory cell unit is formed by connecting said plurality of said memory cells in series, or connecting said plurality of said memory cells in parallel.

19. A semiconductor memory device according to claim 17, wherein said word lines are divided into word blocks each having a plurality of continually numbered word lines to be connected to said memory unit, each of said word blocks is alternately connected to main word line drivers provided at both sides of said memory cell array every one block or every two blocks.

20. A semiconductor memory device according to claim 17, wherein the row selecting means is provided at both sides of said memory cell array to correspond to said word line driver.

21. A semiconductor memory device according to claim 17, wherein only one of the driver circuits provided at the right and left of the memory cell array is selected to be operated during data erasing/writing.

22. A semiconductor memory device according to claim 20, further comprising a signal line for supplying an output signal sent from said row selecting means to said word line driver, wherein said signal line does not cross said memory cell array.

23. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cell units arrayed in a matrix form, said memory cell unit having a plurality of memory cells connected;

word lines for selecting said memory cell;

a plurality of main row decoders and main word line drivers provided at both sides of said memory cell array;

a spare memory cell array for saving a defective cell of said memory cell array;

a plurality of spare word line drivers arranged at both sides of said spare memory cell array; and

a defect saving circuit for storing an address of a detective cell to select said spare word line driver in a case where an inputted address coincides the address of the defective cell, wherein the word lines selected by said main row decoders and driven by said main word line drivers are divided into blocks each having a plurality of continuous word lines, and the word lines of the same block are selected by the same main row decoder.

24. A semiconductor memory device according to claim 23, wherein each of said word blocks is alternately connected to main word line drivers provided at both sides of said memory cell array every one block or every two blocks.

25. A semiconductor memory device according to claim 23, wherein said defect saving circuit saves the defective cell every main row decoder or every multiple of the main row decoder.

26. A semiconductor memory device according to claim 23, wherein said main row decoder selects the block of the memory cell or the multiple of the block.

27. A semiconductor memory device according to claim 23, wherein said defect saving circuit stores an address of the defective cell corresponding to the main word line driver on each side of the memory cell array, separately.