Fair prioritized scheduling in an input-buffered switch
First Claim
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1. An apparatus for scheduling input buffers of fixed size packet switches, including asynchronous transfer mode (ATM) switches, having input and output ports, the apparatus comprising:
- a plurality of input buffers having associate virtual circuits for receiving the arriving cells, each input buffer associated with a respective input port;
a cell switching fabric for processing the received cells from the input buffers to the output ports; and
a scheduling control circuit which uses timestamps associated with the virtual circuits for controlling the processing of the received cells through the cell switching fabric using fair arbitration round robin (FARR) to allow each virtual circuit to receive a fair share of bandwidth.
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Abstract
A Fair Arbitrated Round Robin (FARR) method is disclosed for scheduling the crossbar of an input-buffered asynchronous transfer mode (ATM) switch using an arbiter. Per-virtual-circuit queuing of ATM cells is performed.
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Citations
23 Claims
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1. An apparatus for scheduling input buffers of fixed size packet switches, including asynchronous transfer mode (ATM) switches, having input and output ports, the apparatus comprising:
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a plurality of input buffers having associate virtual circuits for receiving the arriving cells, each input buffer associated with a respective input port; a cell switching fabric for processing the received cells from the input buffers to the output ports; and a scheduling control circuit which uses timestamps associated with the virtual circuits for controlling the processing of the received cells through the cell switching fabric using fair arbitration round robin (FARR) to allow each virtual circuit to receive a fair share of bandwidth. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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2. An apparatus for scheduling input buffers of fixed size packet switches, including asynchronous transfer mode (ATM) switches, having input ad output ports, the apparatus comprising:
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a plurality of input buffers for receiving arriving cells, each input buffer is associated with a respective input port and includes a service list associated with each priority level for each output port; a cell switching fabric for processing the received cells from the input buffers to the output ports; a plurality of queues, each queue associated with a virtual circuit connecting the input buffer with at least one output port and having an associated timestamp; and a scheduling control circuit which uses the timestamps to generate a matching of input buffers to output ports to control the processing of the received cells through the cell switching fabric using a fair arbitration round robin (FARR) program. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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3. A method for scheduling input buffers of fixed size packet switches, including asynchronous transfer mode (ATM) switches, having input and output ports, the method comprising the steps of:
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receiving cells in the input buffers; pre-selecting at each input buffer a virtual circuit for each output port; performing request processing to send a timestamp associated with each pre-selected virtual circuit to a scheduling control circuit; generating a matching of the input buffers to the output ports from the scheduling control circuit using the timestamps; and processing the received cells through a cell switching fabric to the output ports using the matching. - View Dependent Claims (4, 5, 6, 7, 8, 9)
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Specification