Error back-propagation method and neural network system

• US 5,517,598 A
• Filed: 01/28/1993
• Issued: 05/14/1996
• Est. Priority Date: 11/25/1988
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Sirat, Jacques A.
• Primary Examiner(s): Downs, Robert W.
• Application Number:
  US08/275,911
• Time in Patent Office: 1,202 Days
• Field of Search: 395/27
• US Class Current: 706/41
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology

Abstract

Method and apparatus of error back-propagation for use in a neural network system. A first group (11) of processing devices (13₁, 13₂, 13₃) performs the resolving steps and a second group (12) of analogous processing devices (13₄, 13₅) performs the training steps while backpropagating errors calculated in a central processing device (10). The synaptic coefficient matrix C_ij of the first group and the transposed matrix T_ji of the second group are simultaneously updated. This updating of the synaptic coefficients can be performed by means of multipliers (34₁ to 34_N) and adders (37₁ to 37_N).

Claims

1. A neural network device for receiving a signal representing an ambiguous external stimulus, and performing artificial recognition, learning and updating by reiteratively comparing the signal to a signal representing an unambiguous stimulus comprising:

a) feedforward resolving means comprising an input for receiving the comparative and external stimulus signals and a first plurality of processors (1, . . . , N) arranged in a layered architecture of K successive layers, for determining neuron output states V_j^k for each successive layer, each processor comprising;

i) first data input means connected to the input of the resolving means for receiving input data;

ii) data output means for supplying output data;

each processor N_k having its first data input means coupled to the data output means of a preceding processing layer N_K-1,

iii) a read/write coefficient memory for storing a group of values of synaptic coefficients for weighting input data received at the first data input means;

iv) calculating means coupled to the coefficient memory and the first data input means for weighting the input data by the synaptic coefficients and for linearly combining the weighted input data for generating the output data;

v) second data input means for providing coefficient matrix update data;

vi) multiplier means having

A) first multiplier input means coupled to the first data input means for receiving the input data,

B) second multiplier input means coupled to the second data input means, and

C) multiplier output means for supplying updates, the multiplier means multiplying in parallel the input data by the input received at the second multiplier input;

vii) memory control means coupled between the coefficient memory and the multiplier means for generating respective sums by adding respective ones of the updates to respective ones of the values of the synaptic coefficients and also including means for replacing the values in the coefficient memory by the sums;

b) a central processing device having a main input coupled to the output of the last processor (N) for, upon detection of a discrepancy between desired output and device generated output data, supplying at the main output of the central processing device an error signal representative of the discrepancy;

c) an error back-propagation means comprising a second plurality of further processors (1, . . . , N-1) arranged in a layered architecture of successively descending layers, each successive further processor comprising;

i) first error input means connected to the central processing device output for receiving the error signal;

ii) error output means for supplying output error data to the next successive processor;

the first further processor having its first error input means coupled to the main output of the central processing device and to a next further processor, each next further processor having its first error input means coupled to the error output of a preceding further processor, each further processor also comprising;

iii) a further coefficient memory for storing a transpose matrix of synaptic coefficients for weighting component input error data received at the first error input means;

iv) further calculating means coupled to the further coefficient memory and the first error input means for weighting the input error components by the synaptic coefficients of the transpose matrix and for linearly combining the weighted input error components for generating the output error data;

v) second error input means for receiving transpose matrix coefficient updating;

vi) further multiplier means including

A) first multiplier input means coupled to the first error input means for receiving the input error components,

B) second multiplier input means coupled to the second error input means, and

C) multiplier output means for supplying further transpose matrix updates,

the further multiplier means multiplying in parallel the input error components by input received at the second multiplier input means;

vii) further memory control means coupled between the further coefficient memory and the further multiplier means for generating respective further sums by adding respective ones of the further updates to respective ones of the values of the synaptic coefficients and replacing the values in the further coefficient memory by the further sums;

at least one of the second data input means in the resolving means being coupled to receive a value supplied at one of the error output means in the backpropagation means; and

at least one of the second error input means in the backpropagation means being coupled to receive a value produced at one of the data output means in the resolving means.

2. The neural network of claim 1 wherein:

the memory control means in each processing means comprises an adder arrangement for generating the sums in parallel and for replacing in parallel the values in the coefficient memory by the sums; and

the further memory control means in each further processing means comprises a further adder arrangement for generating the further sums in parallel and for replacing in parallel the values in the further coefficient memory by the further sums.

3. The neural network of claim 2 wherein the processing means and the further processing means are all substantially identical.

4. The neural network of claim 1 wherein:

each processing means comprises a data register, coupled between the first data input and the first multiplier input, for storing the input data components; and

each further processing means comprises an error register, coupled between the first error input and the first multiplier input, for storing the input error components.

5. The neural network of claim 4 wherein the processing means and the further processing means are all substantially identical.

6. The neural network of claim 1 wherein:

each processing means comprises an additional register, coupled between the second data input and the second multiplier input, for storing a particular output error component supplied by a related one of the further processing means of the backpropagation path; and

each further processing means comprises a further additional register, coupled between the second error input and the second multiplier input, for storing a particular output data component supplied by an associated one of the processing means of the resolving path.

7. The neural network of claim 6 wherein the processing means and the further processing means are all substantially identical.

8. The neural network of claim 1 wherein:

in each processing means the calculation means performs the weighting of the input data components in parallel, the multiplier arrangement being a functional part of the calculation means; and

in each further processing means the further calculation means performs the weighting of the input error components in parallel, the further multiplier arrangement being a functional part of the further calculation means.

9. The neural network of claim 8 wherein the processing means and the further processing means are all substantially identical.

10. The neural network of claim 1 wherein the processing means and the further processing means are all substantially identical.

11. The network of claim 1 in which in each processing means the synaptic coefficients stored in the coefficient memory form a matrix of coefficients and in each further processing means the synaptic coefficients stored in the coefficient memory form a transpose of one of the matrices.

12. The network of claim 1 in which each of the processors and the further processors comprise vector processors for updating the synaptic coefficients of the C_ij matrices and the T_ji matrices in the resolving phase and the training phase, respectively, and the input data, the output data, the input error data, and the output error data are all in the form of vectors with components supplied in parallel.

13. The neural network device of claim 1 in which each of the first and second plurality of processors comprises memory control means, the memory control means further comprising an adder arrangement for generating the sums in parallel and for replacing in parallel the values in the coefficient memory by the sums.

14. The neural network device of claim 1 in which each of the first plurality of processors further comprises a respective data register, coupled between the first data input and the first multiplier input, for storing the input data components.

15. The neural network device of claim 1 in which each of the first plurality of processors further comprises an additional register, coupled between the second data input and the second multiplier input, for storing vector state data which originates from an external processing device.

16. The neural network of claim 1 in which the calculating means comprises means for performing the weighting of the input data components in parallel, and, the multiplier arrangement is a part of the calculating means.

17. A processor for reiteratively receiving, processing and outputting data related to signal components representing an ambiguous external stimulus and for performing artificial recognition, learning and updating by repetitively comparing the signal components no signal components representing an unambiguous stimulus comprising:

i) first data input means for receiving input data;

ii) data output means for supplying output data;

iii) a read/write coefficient memory for storing a group of values of synaptic coefficients for weighting input data received at the first data input;

iv) calculation means for weighting the input data by the synaptic matrix coefficients and for linearly combining the weighted input data components for generating the output data;

v) second data input means for receiving matrix coefficient update data;

vi) multiplier means including

A) first multiplier input means coupled to the first data input means for receiving the input data components,

B) second multiplier input means coupled to the second data input means, and

C) multiplier output means for supplying updates, the multiplier means multiplying in parallel the input data components by data received at the second multiplier input; and

vii) memory control means coupled between the coefficient memory and the multiplier means for generating respective sums by adding respective ones of the updates to respective ones of the values of the synaptic coefficients and replacing the values in the coefficient memory by the sums.

18. The processor device of claim 17 wherein the memory control means comprises an adder arrangement for generating the sums in parallel and for replacing in parallel the values in the coefficient memory by the sums.

19. The processor device of claim 17 comprising a respective data register, coupled between the first data input and the first multiplier input, for storing the input data components.

20. The processor of claim 17 comprising an additional register, coupled between the second data input and the second multiplier input, for storing vector state data which originates from an external processing device.

21. The processor of claim 17 wherein the calculation means performs the weighting of the input data components in parallel, the multiplier arrangement being a functional part of the calculation means.