Neuro-chip and neurocomputer having the chip

• US 5,517,600 A
• Filed: 08/03/1994
• Issued: 05/14/1996
• Est. Priority Date: 03/01/1990
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimokawa, Yoshiyuki
• Primary Examiner(s): Treat, William M.
• Application Number:
  US08/285,767
• Time in Patent Office: 650 Days
• Field of Search: 395/27, 395/800, 395/24, 395/21, 395/200.03
• US Class Current: 706/15
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A neuro-chip comprising a plurality of neuron operation circuits, a broadcast bus terminal for supplying data in parallel to the neuron operation circuits and receiving data in parallel therefrom, a program data bus connected to the neuron operation circuits, a program data bus terminal for supplying a common program externally input, to the neuron operation circuits through the program data bus, a ring bus connecting the neuron operation circuits, and a plurality of ring bus terminals connected to the ring bus, for transferring data among the neuron operation circuits.

Claims

1. A neuro-chip which comprises:

a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip;

a broadcast bus connected to each of said neuron operation circuit means which broadcasts data between each of said neuron operation circuit means;

a program data bus connected to each of said neuron operation circuit means which supplies a common program externally input to each of said neuron operation circuit means; and

a pair of ring bus terminals connected to said connecting neuron operation circuit means, for transferring data among said connecting neuron operation circuit means of said neuro-chip and said other neuron operation circuit means which are not a part of said neuro-chip through a ring bus.

2. The neuro-chip according to claim 1, wherein each of said neuron operation circuit means includes a control circuit having a flag means which renders the common program not executable, in accordance with a status signal.

3. The neuro-chip according to claim 1, wherein each of said neuron operation circuit means includes a plurality of counter means for counting a number of repetitions of the common program with an instruction and a control circuit means for starting and stopping the execution of the instruction.

4. A neuro-chip which comprises:

a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two of said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip;

a broadcast bus connected to each of said neuron operation circuit means which broadcasts data between each of said neuron operation circuit means;

a program data bus connected to each of said neuron operation circuit means which supplies a common program externally input to each of said neuron operation circuit means; and

a pair of ring bus terminals connected to said connecting neuron operation circuit means, for transferring data among said connecting neuron operation circuit means of said neuro-chip and said other neuron operation circuit means which are not a part of said neuro-chip through a ring bus,

wherein each of said neuron operation circuit means includes;

program hold/interpret means for holding and interpreting the common program;

operation means for executing an instruction output by said program hold/interpret means;

a broadcast bus interface connected to said broadcast bus;

a ring bus interface connected to said ring bus;

a memory for storing data representing a weight assigned to said neuron operation circuit means and holding data output by said operation means; and

a memory interface connected to said memory.

5. The neuro-chip according to claim 4, wherein each of said neuron operation circuit means further includes a control circuit having a flag means which renders the common program not executable, in accordance with a status signal.

6. The neuro-chip according to claim 4, wherein each of said neuron operation circuit means further includes a plurality of counter means for counting a number of repetitions of the common program with an instruction and a control circuit means for starting and stopping the execution of the instruction.

7. A neuro-chip which comprises:

a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two of said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip;

a broadcast bus connected to each of said neuron operation circuit means which broadcasts data between each of said neuron operation circuit means;

a program data bus connected to each of said neuron operation circuit means which supplies a common program externally input to each of said neuron operation circuit means;

a pair of ring bus terminals connected to said connecting neuron operation circuit means, for transferring data among said connecting neuron operation circuit means of said neuro-chip and said other neuron operation circuit means which are not a part of said neuro-chip through a ring bus, and

a memory for storing data representing a weight assigned to each of said neuron operation circuit means and holding data output by said neuron operation circuit means,

wherein each of said neuron operation circuit means includes;

program hold/interpret means for holding and interpreting the common program;

a broadcast bus interface connected to said broadcast bus;

a ring bus interface connected to said ring bus;

a memory interface connected to said memory; and

operation means for executing an instruction output by said program hold/interpret means.

8. The neuro-chip according to claim 7, wherein each of said neuron operation circuit means further includes a control circuit having a flag means which renders the common program not executable in accordance with a status signal.

9. The neuro-chip according to claim 7, wherein each of said neuron operation circuit means further includes a plurality of counter means for counting a number of repetitions of the common program with an instruction and a control circuit means for starting and stopping the execution of the instruction.

10. A neurocomputer which comprises:

a processor for controlling components of the neurocomputer;

a memory provided for said processor;

a program memory provided for said processor;

a plurality of neuron operation circuit means, each of said neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers, at least two of said plurality of neuron operation circuit means being connecting neuron operation circuit means for connection with other neuron operation circuit means which are not a part of said neuro-chip;

a program memory provided in common for said neuron operation circuit means;

a plurality of memories provided for said neuron operation circuit means, respectively;

a broadcast bus connecting said processor to said neuron operation circuit means, for transferring data between said processor and said neuron operation circuit means;

a ring bus connecting said neuron operation circuit means, for transferring data among said neuron operation circuit means; and

a program data bus for supplying a program from said program memory to each of said neuron operation circuit means.

11. A neuro-chip which comprises:

a first neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers;

a broadcast bus terminal for broadcasting a first data from said first neuro operation circuit means through a broadcast bus to a connecting neuron operation circuit means of another neuro-chip, said connecting neuron operation circuit means for simulating neurons, for learning, and for functioning as a neuron arranged in a plurality of layers;

a program data bus terminal for supplying a common program externally input to said first neuron operation circuit means; and

a ring bus terminal, connected to said first neuron operation circuit means, for transferring a second data between said first neuron operating circuit means and said connecting neuron operation circuit means using a ring bus.

12. The neuro-chip according to claim 11, wherein each of said neuron operation circuit means of said neuro-chip includes a control circuit having a flag means which renders the common program not executable, in accordance with a status signal.

13. The neuro-chip according to claim 11, wherein each of said neuron operation circuit means includes a plurality of counter means for counting a number of repetitions of the common program with an instruction and a control circuit means for starting and stopping the execution of the instruction.

14. The neuro-chip according to claim 11, wherein said first neuron operation circuit means includes:

program hold/interpret means for holding and interpreting the common program;

operation means for executing an instruction output by said program hold/interpret means;

a broadcast bus interface connected to said broadcast bus;

a ring bus interface connected to said ring bus;

a memory for storing data representing a weight assigned to said neuron operation circuit means and holding data output by said operation means; and

a memory interface connected to said memory.