System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus

• US 5,517,671 A
• Filed: 07/30/1993
• Issued: 05/14/1996
• Est. Priority Date: 07/30/1993
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Gaskins, Darius D., Parks, Terry J.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PERVEEN, REHANA
• Application Number:
  US08/100,714
• Time in Patent Office: 1,019 Days
• Field of Search: 395/275, 395/725, 395/325, 395/821, 395/823, 395/200.01, 395/427, 395/860, 395/287
• US Class Current: 710/40
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A system for connecting a plurality of input/output (I/O) channels to a single computer system bus. A system controller establishes priority among the I/O channels competing for access to the system bus. A plurality of I/O channel bridges are connected to the system bus and interface with EISA channels. The I/O bridges receive data from the EISA channels at one data rate and transmit the data to the system bus at another data rate. Data is stored within the I/O bridges in a cache memory device until commanded to transmit the data to the system bus by the system controller.

Claims

1. A system for connecting a plurality of input/output (I/O) channels to a single system bus, which I/O channels compete for access to said single system bus, each of said I/O channels transferring data at an individual first rate, said single system bus transferring data at a second rate, each of said individual first rates being slower than said second rate, said system comprising:

a system controller coupled to said single system bus for establishing priority among said plurality of I/O channels competing for access to said single system bus and for allowing data signals therefrom to be transmitted to said single system bus; and

a plurality of I/O channel bridges, each of said plurality of I/O channel bridge connected in circuit between said single system bus and an associated one of said plurality of I/O channels, each of said plurality of I/O channel bridges comprising structure for decoupling transfers of data on its associated I/O channel from said single system bus, which structure for decoupling comprises at least one cache buffer in which said transfers of data on said associated I/O channel are stored until said system controller allows said transfers of data from said associated I/O channel to proceed on said single system bus,

wherein address and control information are also transferred;

wherein each of said plurality of I/O channel bridges further comprises a buffer controller through which said address and control information pass between said plurality of I/O channels and said single system bus, and which buffer controller controls operation of said at least one cache buffer;

wherein said at least one cache buffer is incorporated into at least one first application specific integrated circuit;

wherein said buffer controller is incorporated into a second application specific integrated circuit;

wherein said transfers of data comprise data bits carried on data signals;

wherein said at least one first application specific integrated circuit comprises two first application specific integrated circuits, each of which is coupled to a first number of I/O channel data signals and to a second, larger, number of single system bus data signals;

wherein each of said transfers of data stored within said cache buffers has an associated address;

wherein said second application specific integrated circuit comprises buffer analogs for said cache buffers so that said associated addresses are represented within said second application specific integrated circuit in an ordered manner, which ensured address memory coherency;

wherein said transfers of data, address and control information are transferred in cycles and further comprise interrupt communication cycles; and

wherein said second application specifies integrated circuit further comprises structure for ensuring said interrupt communication cycles are ordered with respect to non-interrupt communication cycles.

2. A system for connecting a plurality of input/output (I/O) channels to a single system bus, which I/O channels compete for access to said single system bus, each of said I/O channels transferring data at an individual first rate, said single system bus transferring data at a second rate, each of said individual first rates being slower than said second rate, said system comprising:

a system controller coupled to said single system bus for establishing priority among said plurality of I/O channels competing for access to said single system bus and for allowing data signals therefrom to be transmitted to said single system bus; and

a plurality of I/O channel bridges, each of said plurality of I/O channel bridge connected in circuit between said single system bus and an associated one of said plurality of I/O channels, each of said plurality of I/O channel bridges comprising structure for decoupling transfers of data on its associated I/O channel from said single system bus, which structure for decoupling comprises at least one cache buffer in which said transfers of data on said associated I/O channel are stored until said system controller allows said transfers of data from said associated I/O channel to proceed on said single system bus,

wherein said transfers of data have associated transfers of address and control information;

wherein each of said plurality of I/O channel bridges further comprises a buffer controller through which said address and control information pass between said plurality of I/O channels and said single system bus, and which buffer controller controls operation of said at least one cache buffer;

wherein said at least one cache buffer is incorporated into at least one first application specific integrated circuit;

wherein said buffer controller is incorporated into a second application specific integrated circuit;

wherein said transfers of data comprise data bits carried on data signals;

wherein said at least one first application specific integrated circuit comprises two first application specific integrated circuits, each of which is coupled to a first number of I/O channel data signals and to a second, larger, number of single system bus data signals; and

wherein said at least one cache buffer comprises two cache buffers in each of said first application specific integrated circuits.

3. A computer system including a system bus, a plurality of input/output (I/O) channels connected to the system bus, and a processor system connected to the system bus, wherein the I/O channels compete for access to and communicate with the system bus, wherein the processor system includes a plurality of processors, each of which communicate with the system bus, and wherein the communications with the system bus comprises data and addresses, the computer system comprising:

a system controller, coupled to said system bus for establishing priority among said plurality of I/O channels competing for access to said system bus and for allowing data signals to be transmitted to said system bus from said I/O channels;

a plurality of I/O channel bridges, each of said plurality of I/O channel bridges connected between said system bus and an associated one of said plurality of I/O channels, wherein each of said plurality of I/O channel bridges decouples transfers of data on its associated I/O channel from said system bus;

a global address mapping system, connected to said system bus, for mapping said addresses to said plurality of I/O channels, comprising;

devices, partitioned among each of said plurality of I/O channels;

descriptors, allied with said partitioned devices, for designating which of said devices is associated with each of said plurality of I/O channels so that said addresses can be mapped to the appropriate one of said plurality of I/O channels wherein said devices comprise I/O devices having an I/O address space and wherein said descriptors further designate which portions of the I/O address space is associated with each of said plurality of I/O channels.

4. The computer system of claim 3, wherein one of said plurality of I/O channels is capable of generating an interrupt request, and wherein said I/O channel bridges further comprise:

a first circuit, coupled to one of said plurality of I/O channel bridges, for receiving said interrupt request for said associated one of said plurality of I/O channels;

a second circuit, coupled to said first circuit, for determining a processor-associated vector for said interrupt request; and

a third circuit, coupled to said one of said plurality of I/O channel bridges, for packaging said processor-associated vector into an interprocessor communication message.

5. The computer system of claim 4 wherein said system controller further comprises:

receiving circuitry, coupled to said system controller, for receiving said interprocessor communication message from said one of said plurality of I/O channel bridges;

decoding circuitry, coupled to said receiving circuitry, for decoding said interprocessor communication message and obtaining said processor associated vector; and

transmitting circuitry, coupled to said decoding circuitry and to said processor system for transmitting said processor-associated vector to said processor system.

6. The computer system of claim 5 wherein said transmitting circuitry transmits said processor-associated vector to an appropriate processor within said processor system.

7. A computer system including a system bus, a plurality of input/output (I/O) channels connected to the system bus, and a processor system connected to the system bus, wherein the I/O channels compete for access to and communicate with the system bus, wherein the processor system includes a plurality of processors, each of which communicate with the system bus, and wherein the communications with the system bus comprises data and addresses, the computer system comprising:

a system controller, coupled to said system bus for establishing priority among said plurality of I/O channels competing for access to said system bus and for allowing data signals to be transmitted to said system bus from said I/O channels;

a plurality of I/O channel bridges, each of said plurality of I/O channel bridges connected between said system bus and an associated one of said plurality of channels, wherein each of said plurality of I/O channel bridges decouples transfers of data on its associated I/O channel from said system bus;

a global address mapping system, connected to said system bus, for mapping said addresses to said plurality of I/O channels, comprising;

devices, partitioned among each of said plurality of I/O channels;

descriptors, allied with said partitioned devices, for designating which of said devices is associated with each of said plurality of I/O channels so that said addresses can be mapped to the appropriate one of said plurality of I/O channels;

wherein said devices comprise memory having an address space and wherein said descriptors further designate which portions of the memory address space is associated with each of said plurality of I/O channels.