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System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus

  • US 5,517,671 A
  • Filed: 07/30/1993
  • Issued: 05/14/1996
  • Est. Priority Date: 07/30/1993
  • Status: Expired due to Term
First Claim
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1. A system for connecting a plurality of input/output (I/O) channels to a single system bus, which I/O channels compete for access to said single system bus, each of said I/O channels transferring data at an individual first rate, said single system bus transferring data at a second rate, each of said individual first rates being slower than said second rate, said system comprising:

  • a system controller coupled to said single system bus for establishing priority among said plurality of I/O channels competing for access to said single system bus and for allowing data signals therefrom to be transmitted to said single system bus; and

    a plurality of I/O channel bridges, each of said plurality of I/O channel bridge connected in circuit between said single system bus and an associated one of said plurality of I/O channels, each of said plurality of I/O channel bridges comprising structure for decoupling transfers of data on its associated I/O channel from said single system bus, which structure for decoupling comprises at least one cache buffer in which said transfers of data on said associated I/O channel are stored until said system controller allows said transfers of data from said associated I/O channel to proceed on said single system bus,wherein address and control information are also transferred;

    wherein each of said plurality of I/O channel bridges further comprises a buffer controller through which said address and control information pass between said plurality of I/O channels and said single system bus, and which buffer controller controls operation of said at least one cache buffer;

    wherein said at least one cache buffer is incorporated into at least one first application specific integrated circuit;

    wherein said buffer controller is incorporated into a second application specific integrated circuit;

    wherein said transfers of data comprise data bits carried on data signals;

    wherein said at least one first application specific integrated circuit comprises two first application specific integrated circuits, each of which is coupled to a first number of I/O channel data signals and to a second, larger, number of single system bus data signals;

    wherein each of said transfers of data stored within said cache buffers has an associated address;

    wherein said second application specific integrated circuit comprises buffer analogs for said cache buffers so that said associated addresses are represented within said second application specific integrated circuit in an ordered manner, which ensured address memory coherency;

    wherein said transfers of data, address and control information are transferred in cycles and further comprise interrupt communication cycles; and

    wherein said second application specifies integrated circuit further comprises structure for ensuring said interrupt communication cycles are ordered with respect to non-interrupt communication cycles.

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