Fabrication processes for monolithic electronic modules

• US 5,517,754 A
• Filed: 06/02/1994
• Issued: 05/21/1996
• Est. Priority Date: 06/02/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Howell, Wayne J., Beilstein, Kenneth E. Jr.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/252,794
• Time in Patent Office: 719 Days
• Field of Search: 269/903, 437/208, 437/974, 437/209, 437/51, 257/777
• US Class Current: 29/840
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: Y10S 269/903 Work holder for electrical circuit assemblages or wiring systems
• CPC Class Codes: Y10S 269/909 Work holder for specific work
• CPC Class Codes: Y10S 428/914 Transfer or decalcomania
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 428/14 Layer or component removable to expose adhesive
• CPC Class Codes: Y10T 428/1438 Metal containing
• CPC Class Codes: Y10T 428/1481 Dissimilar adhesives
• CPC Class Codes: Y10T 428/24942 including components having same physical characteristic in differing degree

Abstract

This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

Claims

1. A process for metallizing a selected side surface of each electronic module of multiple electronic modules, said metallizing process comprising the steps of:

(a) forming a stack including said multiple electronic modules such that the selected side surfaces of the multiple electronic modules are coplanar, said forming of the stack including utilizing a workpiece between two adjacent electronic modules in the stack, said workpiece having a first side surface corresponding to the coplanar selected side surfaces of the multiple electronic modules, said first side surface of said workpiece having at least a region that is non-coplanar with the coplanar selected side surfaces of the multiple electronic modules; and

(b) metallizing said selected side surfaces of the multiple electronic modules in said stack to form a stack metallization pattern, said stack metallization pattern being automatically discontinuous at said region of non-coplanarity of said first side surface of said workpiece with said coplanar selected side surfaces of the multiple electronic modules.

2. The metallizing process of claim 1, wherein each electronic module of said multiple electronic modules comprises a semiconductor chip, and wherein said forming step (a) includes utilizing multiple workpieces in said stack, each workpiece being disposed between two adjacent semiconductor chips in the stack.

3. The metallizing process of claim 1, wherein each electronic module of said multiple electronic modules comprises n semiconductor chips, wherein n is an integer ≧

2, and wherein said forming step (a) includes forming each electronic module of said multiple electronic modules by laminating together n semiconductor chips simultaneous with forming said stack.

4. The metallizing process of claim 3, wherein each semiconductor chip of said n semiconductor chips in each electronic module of said multiple electronic modules has two substantially parallel main surfaces, and wherein said forming step (a) includes, for each electronic module of said multiple electronic modules, laminating said n semiconductor chips together such that a main surface of each semiconductor chip is laminated to a main surface of an adjacent semiconductor chip.

5. The metallizing process of claim 1, further comprising the step of segmenting said stack at said workpiece, said segmenting of said stack at said workpiece being subsequent to said metallizing step (b) and occurring at said automatic discontinuity in the stack metallization pattern.

6. The metallizing process of claim 1, wherein said forming step (a) includes utilizing multiple workpieces such that each workpiece resides between two adjacent electronic modules of the multiple electronic modules in the stack.

7. The metallizing process of claim 1, wherein said forming step (a) further includes creating said region of non-coplanarity in the first side surface of the workpiece, said creating including preferentially removing material from the workpiece such that a trench is formed, said trench comprising the region of non-coplanarity in said first side surface with the selected side surfaces of the multiple electronic modules in the stack.

8. The metallizing process of claim 7, wherein said preferential removing of material includes removing material until the trench has a depth sufficient to prevent bridging of the trench by the stack metallization pattern formed by said metallizing step (b).

9. The metallizing process of claim 1, wherein said workpiece includes a separator substrate having a first main surface and a second main surface, said first main surface and said second main surface being substantially parallel, and said workpiece further includes a layer of separation material disposed on at least one of said first main surface and said second main surface, and wherein said forming step (a) includes preferentially removing a portion of said layer of separation material to define in said first side surface of the workpiece said region of non-coplanarity with the coplanar selected side surfaces of the multiple electronic modules in the stack.

10. The metallizing process of claim 9, wherein said workpiece further comprises a temporary adhesive layer, and wherein said metallizing process further comprises segmenting said stack at said workpiece along said temporary adhesive layer subsequent to said metallizing step (b).

11. The metallizing process of claim 1, further comprising the step of preforming each electronic module of said multiple electronic modules, each electronic module being preformed by laminating n semiconductor chips together, n being an integer ≧

2, such that a main planar surface of each semiconductor chip is secured to a main planar surface of an adjacent semiconductor chip in the electronic module.

12. The metallizing process of claim 11, wherein each electronic module has two end semiconductor chips, and wherein said laminating includes laminating said semiconductor chips such that each end semiconductor chip of the two end semiconductor chips in each electronic module comprises an active semiconductor chip.

13. The metallizing process of claim 12, wherein said forming step (a) includes forming the stack by utilizing multiple workpieces, each workpiece of the multiple workpieces being adhered to an end surface of an adjacent electronic module in the stack.

14. The metallizing process of claim 13, wherein each workpiece is preformed of multiple layers, at least one of said multiple layers comprising a separation material layer, and wherein said forming step (a) includes preferentially removing said separation material layer of each workpiece to define in said first side surface of the workpiece said region of non-coplanarity with the coplanar selected side surfaces of the multiple electronic modules in the stack.

15. The metallizing process of claim 14, further comprising the steps of insulating the selected side surfaces of the multiple electronic modules in the stack and subsequently exposing at the selected side surfaces transfer wirings from at least some semiconductor chips of the semiconductor chips forming each electronic module of the multiple electronic modules in the stack.

16. The metallizing process of claim 15, wherein said metallizing step (b) includes depositing and patterning said stack metallization pattern on said selected side surfaces of the multiple electronic modules without regard to said multiple workpieces disposed in the stack.

17. The metallizing process of claim 16, further comprising the step of segmenting the stack at each workpiece subsequent to said metallizing step (b), said segmenting employing the automatic discontinuity of the stack metallization pattern at the region of non-coplanarity in each first side surface of the multiple workpieces such that the stack is segmented without damaging the stack metallization pattern on the coplanar selected side surfaces of the multiple electronic modules.

18. A process for applying a transfer layer to a planar main surface of a semiconductor chip, said process comprising the steps of:

(a) providing a workpiece having multiple layers, one layer of said multiple layers comprising the transfer layer;

(b) temporarily affixing said workpiece to the planar main surface of the semiconductor chip such that the transfer layer is adhered to the planar main surface of the semiconductor chip; and

(c) separating part of the workpiece from the semiconductor chip, said separating being such that the transfer layer remains adhered to the planar main surface of the semiconductor chip.

19. The process of claim 18, wherein said providing step (a) includes providing the workpiece such that the one layer of the multiple layers comprising the transfer layer is an insulation layer.

20. The process of claim 18, wherein said providing step (a) includes providing the workpiece such that the one layer of the multiple layers comprising the transfer layer is a metallization layer, and said temporarily affixing step (b) includes electrically coupling said metallization layer to the semiconductor chip.

21. The process of claim 20, wherein said electrical coupling of said metallization layer to the semiconductor chip includes providing metal interconnect between the metallization layer and the semiconductor chip such that the metallization layer is electrically coupled to the semiconductor chip.

22. The process of claim 18, wherein the transfer layer comprises an active circuit layer and wherein said temporarily affixing step (b) includes electrically coupling said active circuit layer to the semiconductor chip via metal interconnect.

23. The process of claim 22, wherein said temporarily affixing step (b) includes providing insulation about the metal interconnect electrically coupling the active layer to the semiconductor chip.

24. The process of claim 18, further comprising the step of applying a metallization pattern to a side surface of the semiconductor chip, said applying step being subsequent to said temporarily affixing step (b) and prior to said separating step (c).

25. The process of claim 24, further comprising the step of applying at least one solder bump to said metallization pattern on the side surface of the semiconductor chip prior to said separating step (c).

26. The process of claim 18, wherein multiple transfer layers are to be applied to multiple semiconductor chips such that each transfer layer is applied to a planar main surface of an adjacent semiconductor chip of the multiple semiconductor chips, and wherein said providing step (a) includes providing multiple workpieces, each workpiece having one transfer layer of said multiple transfer layers, and wherein said temporarily affixing step (b) includes forming a stack of said multiple semiconductor chips and said multiple workpieces such that each workpiece of said multiple workpieces is disposed adjacent to a planar main surface of at least one semiconductor chip of the multiple semiconductor chips, wherein the multiple semiconductor chips and the multiple workpieces are interleaved within the stack.

27. A process for metallizing a side surface of a semiconductor chip, said process comprising the steps of:

(a) providing a workpiece;

(b) affixing the workpiece to the semiconductor chip;

(c) directly metallizing the side surface of the semiconductor chip to produce a metallization pattern thereon; and

(d) separating the workpiece from the semiconductor chip without damaging the metallization pattern on the side surface of the semiconductor chip.

28. The process of claim 27, wherein the semiconductor chip has a planar main surface, and wherein said affixing step (b) includes affixing the workpiece to the planar main surface of the semiconductor chip.

29. The process of claim 28, wherein the workpiece has multiple layers and one layer of said multiple layers comprises a transfer layer, and wherein said affixing step (b) includes affixing the workpiece to the semiconductor chip such that the transfer layer remains affixed to the chip subsequent to said separating step (d).

30. The process of claim 29, wherein said providing step (a) comprises providing a workpiece with a transfer layer comprising an insulation layer.

31. The process of claim 29, wherein said providing step (a) includes providing a workpiece with a transfer layer comprising a metallization layer.

32. The process of claim 31, further comprising the step of electrically coupling the metallization layer to at least either the semiconductor chip or the metallization pattern formed on the side surface of the semiconductor chip.

33. The process of claim 29, wherein said providing step (a) includes providing a workpiece having a transfer layer comprising an active circuit layer, and wherein said method further comprises the step of electrically coupling said active circuit layer to at least either the semiconductor chip or said metallization pattern on the side surface of the semiconductor chip.

34. The process of claim 29, wherein said affixing step (b) includes bonding the transfer layer to the semiconductor chip.

35. The process of claim 27, wherein said metallizing step (c) includes providing metal interconnect as part of said metallization pattern for connecting the semiconductor chip to an external circuit.

36. A process for metallizing a selected side surface and an end surface of an electronic module, said process comprising the steps of:

(a) providing a workpiece having multiple layers, one layer of said multiple layers comprising a metallization layer;

(b) temporarily affixing the workpiece to the electronic module such that the metallization layer of the workpiece is bonded to the end surface of the electronic module;

(c) forming a metallization pattern on the selected side surface of the electronic module; and

(d) separating a part of the workpiece from the electronic module such that the metallization layer remains bonded to the end surface of the electronic module.

37. The process of claim 36, further comprising the step of electrically coupling the metallization pattern on the selected side surface of the electronic module with the metallization layer bonded to the end surface of the electronic module.

38. The process of claim 36, wherein said forming step (c) includes forming the metallization pattern on the selected side surface of the electronic module such that the metallization pattern has an extension beyond the end surface of the electronic module partially over the workpiece, said extension of said metallization pattern facilitating electrical coupling of the metallization pattern on the selected side surface with the metallization layer bonded to the end surface of the electronic module.

39. The process of claim 38, wherein said providing step (a) includes providing the workpiece of multiple layers such that one layer of the multiple layers comprises a temporary adhesive layer, and wherein said separating step (d) comprises separating part of the workpiece from the electronic module at said temporary adhesive layer.

40. The process of claim 39, wherein the extension of the metallization pattern on the side surface of the electronic module is substantially equal to a thickness of the temporary adhesive layer of the workpiece.

41. The process of claim 36, wherein said electronic module comprises multiple semiconductor chips, and wherein said forming step (c) including forming the metallization pattern on the selected side surface of the electronic module such that at least some of the multiple semiconductor chips are electrically interconnected.

42. The process of claim 41, wherein the electronic module includes an end semiconductor chip disposed adjacent to the end surface of the electronic module, said end semiconductor chip comprising an active semiconductor chip and wherein said process further comprises the step of electrically coupling the metallization pattern on the selected side surface of the electronic module with the metallization layer bonded to the end surface of the electronic module.