Semiconductor memory device having surrounding gate transistor

• US 5,519,236 A
• Filed: 06/27/1994
• Issued: 05/21/1996
• Est. Priority Date: 06/28/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozaki, Tohru
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/266,389
• Time in Patent Office: 694 Days
• Field of Search: 257/302, 257/401, 257/773, 257/905
• US Class Current: 257/302
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical

Abstract

A semiconductor memory device includes at least one memory cell formed on a substrate. The memory cell is constructed by a hole capacitor and a vertical transistor. The hole capacitor is formed in a hole on the substrate. The vertical transistor is formed in a semiconductor column formed in position adjacent to the hole.

Claims

1. A semiconductor memory device comprising:

a substrate having at least one trench and at least one semiconductor column formed in position adjacent to said trench;

at least one memory cell formed on said substrate, said memory cell being constructed by a trench capacitor and a vertical transistor having a source and drain, said trench capacitor being formed along an inside wall of said trench, with only one electrode of said trench capacitor being formed in the trench, and said vertical transistor being formed in said semiconductor column;

bit line layers and word lines;

wherein a plurality of memory cells are formed on said substrate, a plurality of trench capacitors and a plurality of vertical transistors are arranged in a checkerboard pattern, one electrode of said trench capacitor contacts one of said source and drain of said vertical transistor at only one side of the column, each of said trench capacitors includes a plate electrode formed of said substrate, a storage electrode buried in the trench, and a capacitor insulation film formed between said plate electrode and said storage electrode, and each of said vertical transistors includes a drain region formed in the top portion of said semiconductor column and connected to a corresponding one of said bit line layers, a gate electrode formed on the side surface of said semiconductor column and connected to a corresponding one of said word lines and a source region formed in said semiconductor column below said gate electrode and connected to said storage electrode.

2. The semiconductor memory device according to claim 1, wherein one of said trench capacitors and one of said vertical transistors which constitute one memory cell are disposed adjacent to each other along said word line layer.

3. The semiconductor memory device according to claim 1, wherein said bit line layers are arranged with the width of feature size determined by a minimum processing limit and at an interval of feature size determined by the minimum processing limit and said word line layers are arranged with the width of feature size determined by the minimum processing limit and at an interval of feature size determined by the minimum processing limit.

4. The semiconductor memory device according to claim 3, wherein each of said memory cells is formed at the center portion between adjacent two of said bit line layers.

5. The semiconductor memory device according to claim 3, wherein each of said bit line layer overlaps both of a corresponding one of said trench capacitors and an adjacent one of said vertical transistors.

6. The semiconductor memory device according to claim 3, wherein said drain region is connected to a corresponding one of said bit line layers via a bit line contact and said bit line contact is disposed separately from the end of said drain region.

7. A semiconductor memory device comprising:

a substrate having a plurality of trenches and a plurality of semiconductor columns, aid trenches and said semiconductor columns being arranged in a checkerboard pattern;

a memory cell array having a plurality of memory cells formed on said substrate, each of said memory cells being constructed by a trench capacitor formed in each of said trenches and a vertical transistor, said vertical transistor being formed in a semiconductor column lying adjacent to said trench capacitor;

a plurality of bit line layers which are commonly connected to one of a drain and a source of the vertical transistors; and

a plurality of word line layers which are each formed of two word line layer sections, between which each of said semiconductor columns is placed;

wherein each of said trench capacitors includes a plate electrode formed of said substrate, a storage electrode buried in the trench, and a capacitor insulation film formed between said plate electrode and said storage electrode, and each of said vertical transistors includes a drain region formed in the top portion of said semiconductor column and connected to a corresponding one of said line layers, a gate electrode formed on the side wall of said semiconductor column and connected to a corresponding one of said word line layers and a source region formed in said semiconductor column below said gate electrode and connected to said storage electrode.