Coaxial switch module
First Claim
Patent Images
1. A semiconductor switching device module of reduced inductance comprising:
- a housing having a baseplate and defining a chamber;
a first terminal member having a cylindrical body portion and at least one flange, and also having a first inductance;
a second terminal member having a cylindrical body portion that is coaxial and concentric with said first terminal member body portion and that has at least one flange, and also has a second inductance that is substantially similar to said first inductance;
a plurality of insulating substrates, each of which contains only one insulated gate switching transistor chip;
said substrates disposed in said chamber on said baseplate in a generally symmetrical array that encircles said terminals, including their flanges;
a radially outwardly spacing of each of said substrates from a respective flange portion of each of said terminals, said spacing not being further than about a maximum dimension of one of said chips;
a radially inward input electrical connection between each of said chips and a respective flange portion of one of said terminals;
a radially inward output electrical connection between each of said chips and a respective flange portion of the other of said terminals; and
a spacing between said first and second terminal members, including their flanges, effective to allow said first and second inductances to negate each other.
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Accused Products
Abstract
A low inductance coaxial semiconductor switching module and methods of operating the same. The module can contain high power, high frequency semiconductor switching devices, operated to provide high power at low inductance. The module incorporates compositional, geometrical and electrical symmetry in a coaxial configuration. The module also includes short internal leads, a special circumferential array of substrates, a special circular gate circuit, a special circular kelvin circuit, and special terminal subassembly and special module mounting features.
18 Citations
39 Claims
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1. A semiconductor switching device module of reduced inductance comprising:
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a housing having a baseplate and defining a chamber; a first terminal member having a cylindrical body portion and at least one flange, and also having a first inductance; a second terminal member having a cylindrical body portion that is coaxial and concentric with said first terminal member body portion and that has at least one flange, and also has a second inductance that is substantially similar to said first inductance; a plurality of insulating substrates, each of which contains only one insulated gate switching transistor chip; said substrates disposed in said chamber on said baseplate in a generally symmetrical array that encircles said terminals, including their flanges; a radially outwardly spacing of each of said substrates from a respective flange portion of each of said terminals, said spacing not being further than about a maximum dimension of one of said chips; a radially inward input electrical connection between each of said chips and a respective flange portion of one of said terminals; a radially inward output electrical connection between each of said chips and a respective flange portion of the other of said terminals; and a spacing between said first and second terminal members, including their flanges, effective to allow said first and second inductances to negate each other. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A high power semiconductor device module capable of operating at high frequency and low parasitic losses comprising:
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a housing defining a chamber and including a baseplate and a cover; a first cylindrical terminal conductor of a given composition and having an axis perpendicular to said baseplate and a first outwardly extending circumferential flange, said first flange disposed within said chamber parallel to said baseplate for connection to a plurality of high power insulated gate switching transistors in said chamber, and an end of said first terminal conductor disposed outside said chamber for connection to a first external bus, said first terminal conductor having a given electrical resistance and inductance with respect to electrical current flow therethrough; a second cylindrical terminal conductor including a second flange disposed within said chamber for connection to said plurality of high power insulated gate switching transistors and further including an end of said second terminal conductor disposed outside said chamber for connection to a second external bus, effective to permit coaxial nesting of said first and second cylindrical terminal conductors together in spaced relationship in substantial overlapping disposition of cylindrical body portions and also of flange portions; said insulated gate switching transistors having substantially equal electrical performance characteristics and symmetrically, radially and circumferentially disposed within said chamber in proximity to said first and second flanges for reducing electrical inductance and resistance therebetween; an input electrical connection between each of said insulated gate switching transistors and said first flange to provide symmetry in input connection resistance and inductance; an output electrical connection between each of said insulated gate switching transistors and said second flange to provide symmetry in output connection resistance and inductance; at least a portion of said input and output electrical connections for each insulated gate switching transistor in substantially parallel disposition to each other at least in one plane, and in proximity to reduce net electrical inductance of said input and output electrical connections; a gate conductor means having a first portion disposed within said chamber and adapted to supply substantially equal gate voltage to each of said insulated gate switching transistors, and further having a terminal portion disposed outside said chamber for connection to a source of gate control voltage, said first portion including a circuit pattern in said housing surrounding the symmetrical disposition of said insulated gate switching transistors, said circuit pattern including a gate conductor pattern for said insulated gate switching transistors; and gate electrical connections between gate electrodes on each of said insulated gate switching transistors and said gate conductor means, whereby said transistors each operate at a predetermined current level. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A semiconductor switching device module of reduced inductance comprising:
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a housing defining a chamber; a first terminal member having a cylindrical body portion and at least one flange, and also having a first inductance; a second terminal member that has a cylindrical body portion that is coaxial and concentric with said first terminal member body portion and that further has at least one flange, and also has a second inductance that is substantially similar to said first inductance; a spacing between said first and second terminal members, including their flanges, effective to allow said first and second inductances to negate one another; a plurality of insulating substrates, each of which contains only one insulated gate switching transistor chip; said substrates disposed in said chamber in a generally symmetrical array that encircles said terminals, including their flanges; a radially outwardly spacing of each of said substrates from a respective flange portion of each of said terminals, said spacing not being further than about a maximum dimension of one of said switching transistor chips; and a circuit pattern surrounding the symmetrical array of insulated gate switching transistor chips, said circuit pattern including a gate conductor pattern for said switching transistor chips, an input kelvin conductor pattern and an output kelvin conductor pattern. - View Dependent Claims (28, 29, 30)
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31. A semiconductor switching device module of reduced inductance comprising:
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a housing having a baseplate and defining a chamber; a first terminal member having a cylindrical body portion and at least one radially outwardly circumferential flange, and also having a first inductance; a second terminal member having a cylindrical body portion that is coaxial and concentric with said first terminal member body portion and that has at least one radially outwardly circumferential flange, and also has a second inductance that is substantially similar to said first inductance; a plurality of insulating substrates, each of which contains only one insulated gate switching transistor chip; said substrates disposed in said chamber on said baseplate in a generally symmetrical array that encircles said terminals, including their circumferential flanges; a spacing between said first and second terminal members, including their circumferential flanges, effective to allow said first and second inductances to negate each other; and said terminal members spaced by a dielectric plastic having a cylindrical portion and a flanged portion analogous to that of said coaxial terminal members, said plastic and said terminal members comprising a molded unitary subassembly.
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32. A semiconductor switching device module of reduced inductance comprising:
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a housing having a baseplate and defining a chamber; a first terminal member having a cylindrical body portion and at least one radially outwardly circumferential flange, and also having a first inductance; a second terminal member having a cylindrical body portion that is coaxial and concentric with said first terminal member body portion and that has at least one radially outwardly circumferential flange, and also has a second inductance that is substantially similar to said first inductance; a plurality of insulating substrates, each of which contains only one insulated gate switching transistor chip; said substrates disposed in said chamber on said baseplate in a generally symmetrical array that encircles said terminals, including their circumferential flanges; a spacing between said first and second terminal members, including their circumferential flanges, effective to allow said first and second inductances to substantially negate each other; and the body portion of one of the coaxial terminals is not only disposed within the body portion of the other terminal, but also contains integral mounting bolt means. - View Dependent Claims (33, 34, 35)
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36. A high power semiconductor device module capable of operating at high frequency and low parasitic losses comprising:
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a housing defining a chamber and including a baseplate and a cover; a first cylindrical terminal conductor of a given composition and having an axis perpendicular to said baseplate and a first outwardly extending circumferential flange, said first flange disposed within said chamber parallel to said baseplate for connection to a plurality of high power insulated gate switching transistors in said chamber, and an end of said first terminal conductor disposed outside said chamber for connection to a first external bus, said first terminal conductor having a given electrical resistance and inductance with respect to electrical current flow therethrough; a second cylindrical terminal conductor including a second flange disposed within said chamber for connection to said plurality of high power insulated gate switching transistors and further including an end of said second terminal conductor disposed outside said chamber for connection to a second external bus, effective to permit coaxial nesting of said first and second cylindrical terminal conductors together in spaced relationship in substantial overlapping disposition of cylindrical body portions and also of flange portions; said insulated gate switching transistors having substantially equal electrical performance characteristics and symmetrically, radially and circumferentially disposed within said chamber in proximity to said first and second flanges for reducing electrical inductance and resistance therebetween; an input electrical connection between each of said insulated gate switching transistors and said first flange to provide symmetry in input connection resistance and inductance; an output electrical connection between each of said insulated gate switching transistors and said second flange to provide symmetry in output connection resistance and inductance; at least a portion of said input and output electrical connections for each insulated gate switching transistor in substantially parallel disposition to each other at least in one plane, and in proximity to reduce net electrical inductance of said input and output electrical connections; a gate conductor means having a first portion disposed within said chamber and adapted to supply substantially equal gate voltage to each of said insulated gate switching transistors, and further having a terminal portion disposed outside said chamber for connection to a source of gate control, said first portion including a circuit pattern in said housing surrounding the symmetrical disposition of said insulated gate switching transistors, said circuit pattern including a gate conductor pattern for said insulated gate switching transistors, an input kelvin conductor pattern and an output kelvin conductor pattern; and gate electrical connections between gate electrodes on each of said insulated gate switching transistors and said gate conductor mans, whereby said transistors each operate at a predetermined current level. - View Dependent Claims (37, 38)
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39. A semiconductor switching device module of reduced inductance comprising:
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a housing defining a chamber; a first terminal member having a cylindrical body portion and at least one flange, and also having a first inductance; a second terminal member that has a cylindrical body portion that is coaxial and concentric with said first terminal member body portion and that further has at least one flange, and also has a second inductance that is similar to said first inductance; a spacing between said first and second terminal members, including their flanges, effective to allow said first and second inductances to negate one another; a plurality of insulating substrates, each of which contains only one insulated gate switching transistor chip; said substrates disposed in said chamber in a generally symmetrical array that encircles said terminals, including their flanges; a radially outwardly spacing of each of said substrates from a respective flange portion of each of said terminals, said spacing not being further than about a maximum dimension of one of said switching transistor chips; and a circuit pattern surrounding the symmetrical array of insulated gate switching transistor chips, said circuit pattern including a gate conductor pattern for said switching transistor chips.
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Specification