Method for electrically characterizing the insulator in SOI devices
First Claim
1. A method of determining electrical characteristics of the top silicon to insulator interface in a silicon on insulator (SOI) wafer having a top silicon layer, a buried oxide layer and a silicon substrate, wherein said buried oxide layer is located between said top silicon layer and said silicon substrate, comprising the following steps:
- providing a silicon island in said top silicon layer;
providing a first electrical connection to said silicon substrate to serve as a gate terminal;
providing a second electrical probe connection to a designated drain region in said silicon island;
providing a third electrical probe connection to a designated source region in said silicon island;
applying a first variable gate voltage to said gate terminal;
performing a first series of measurements of drain current as a function of said first variable gate voltage; and
evaluating said first series of measurements of drain current to determine said electrical characteristics.
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Abstract
A rapid method for determining electrical characteristics of SOI wafers whereby the silicon substrate acts as a gate and tungsten probes make a source and drain connection at the top silicon surface to form a point contact transistor. Drain current is measured as a function of gate voltage as gate voltage is swept from negative to positive values. The subthreshold voltage current characteristic exhibits a minimum drain current occurring close to zero gate voltage. The tungsten probe point contacts apparently are responding to both electron and hole conduction or simply intrinsic CMOS behavior. Using current voltage characteristics, estimates may be made of interface state density and oxide charge density. Analysis of the gate voltage shift for minimum drain current allows determination of threshold voltage shift due to radiation.
36 Citations
6 Claims
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1. A method of determining electrical characteristics of the top silicon to insulator interface in a silicon on insulator (SOI) wafer having a top silicon layer, a buried oxide layer and a silicon substrate, wherein said buried oxide layer is located between said top silicon layer and said silicon substrate, comprising the following steps:
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providing a silicon island in said top silicon layer; providing a first electrical connection to said silicon substrate to serve as a gate terminal; providing a second electrical probe connection to a designated drain region in said silicon island; providing a third electrical probe connection to a designated source region in said silicon island; applying a first variable gate voltage to said gate terminal; performing a first series of measurements of drain current as a function of said first variable gate voltage; and evaluating said first series of measurements of drain current to determine said electrical characteristics. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification