Signal synchronized digital frequency discriminator
First Claim
1. A signal-synchronized digital frequency discriminator for digitally processing an optical input signal including first and second time separated optical input pulses to determine if the frequency of any two sequential pulses lies within a predetermined frequency band with upper and lower frequency limits, comprising:
- a. an optical signal detector circuit for receiving the optical input signal consisting of a series of spaced-apart optical pulses and for generating an electrical output signal including output pulses synchronized with the optical input pulses;
b. a delay timer having a pulse detector coupled to sense the output pulses from the optical signal detector for operating in a pulse sensing standby mode prior to receipt of the first pulse, for switching into a time-limited active mode upon receipt of the first pulse to define a fixed duration delay interval having a duration equal to the period of the upper frequency limit of the frequency band, and for switching back into the pulse sensing standby mode upon completion of the delay interval;
c. a gate timer coupled to an output of the delay timer for switching from a standby mode into a time-limited active mode upon completion of the delay interval to define a fixed duration bandwidth interval; and
d. a monitoring circuit having a first input coupled to the pulse detector to monitor the pulses and a second input coupled to monitor an output of the gate timer for generating a frequency coincidence signal when the second pulse is received during the bandwidth interval to indicate that the frequency of the optical input pulses lies within the predetermined frequency band.
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Accused Products
Abstract
A digital frequency discriminator processes input pulses including first and second time separated input pulses to determine if the frequency of any two sequential pulses lie within a predetermined frequency band with upper and lower frequency limits and that they are received for at least a predetermined period of time. A delay timer is coupled to sense the input pulse stream and operates in a pulse sensing standby mode prior to receipt of the first input pulse. Upon receipt of the first input pulse, the delay timer switches into a time-limited active mode to define a fixed duration delay interval having a duration equal to the period of the upper frequency limit of the frequency band. The delay timer switches back into the pulse sensing standby mode upon completion of the delay interval. A gate timer is coupled to the output of the delay timer and switches from a standby mode into a time-limited active mode upon completion of the delay interval to define a fixed duration bandwidth interval. A monitoring circuit includes a first input coupled to monitor the input pulse stream and a second input coupled to monitor the output of the gate timer. The monitoring circuit generates a frequency coincidence signal when the second input pulse is received during the bandwidth interval to indicate that the frequency of the input pulse lies within the predetermined frequency band. A recognition circuit is coupled to monitor the output of the coincidence detector to ensure that the coincidence signal is received for at least a predetermined period of time.
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Citations
44 Claims
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1. A signal-synchronized digital frequency discriminator for digitally processing an optical input signal including first and second time separated optical input pulses to determine if the frequency of any two sequential pulses lies within a predetermined frequency band with upper and lower frequency limits, comprising:
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a. an optical signal detector circuit for receiving the optical input signal consisting of a series of spaced-apart optical pulses and for generating an electrical output signal including output pulses synchronized with the optical input pulses; b. a delay timer having a pulse detector coupled to sense the output pulses from the optical signal detector for operating in a pulse sensing standby mode prior to receipt of the first pulse, for switching into a time-limited active mode upon receipt of the first pulse to define a fixed duration delay interval having a duration equal to the period of the upper frequency limit of the frequency band, and for switching back into the pulse sensing standby mode upon completion of the delay interval; c. a gate timer coupled to an output of the delay timer for switching from a standby mode into a time-limited active mode upon completion of the delay interval to define a fixed duration bandwidth interval; and d. a monitoring circuit having a first input coupled to the pulse detector to monitor the pulses and a second input coupled to monitor an output of the gate timer for generating a frequency coincidence signal when the second pulse is received during the bandwidth interval to indicate that the frequency of the optical input pulses lies within the predetermined frequency band. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A signal-synchronized digital signal discriminator for providing a control signal only in response to an input signal lying within a predetermined frequency range with upper and lower frequency limits wherein the input signal is present for a predetermined period of time, the discriminator comprising:
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a. a first non-retriggerable logic circuit with an input coupled to receive the input signal for generating an output pulse having a pulse duration set equal to the period of the upper frequency limit; b. a second logic circuit with an input operatively connected to the output of the first logic circuit for generating an output pulse with a pulse duration determining the bandwidth of the discriminator; c. a coincidence detector having a first input coupled to the input of the first logic circuit and a second input coupled to the output of the second logic circuit for comparing the input of the first logic circuit to the output of the second logic circuit and for generating a coincidence signal when the inputs occur simultaneously; d. a third non-retriggerable resettable logic circuit having a pulse duration set to determine the predetermined period of time and having an input coupled to receive the coincidence signal; e. a fourth retriggerable logic circuit with a pulse duration set to be slightly longer than the period of the lower frequency limit and having an input operatively connected to the output of the coincidence detector; f. reset means coupled to sense the output state of the third and fourth logic circuits for resetting the third logic circuit if the fourth logic circuit changes state before the third logic circuit changes state; and g. a recognition detector coupled to the third and fourth logic circuits to generate the control signal when the third logic circuit changes state before the fourth logic circuit changes state. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A method for digitally processing an input pulse stream including a series of sequential pulses to determine if the frequency of any two sequential pulses lies within a predetermined frequency band comprising the steps of:
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a. operating a pulse detector in a pulse sensing standby mode prior to receipt of the first input pulse; b. disabling the pulse detector and switching into a time-limited active mode upon receipt of the first input pulse and defining a fixed duration delay interval commencing upon receipt of the first input pulse; c. resetting the pulse detector to operate in the pulse sensing standby mode upon completion of the delay interval; d. defining a bandwidth interval commencing upon completion of the delay interval; e. generating a frequency coincidence signal when the second input pulse is sensed during the bandwidth interval to indicate that the frequency of the input pulse train lies within the predetermined frequency band; and f. receiving the frequency coincidence signal and generating a recognition signal upon receiving successive frequency coincidence signals for at least a predetermined time interval. - View Dependent Claims (43, 44)
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Specification