Circuit for processing the output signal from a resistive analog sensor, in particular for the fuel gauge of a motor vehicle, and systems fitted therewith

• US 5,519,397 A
• Filed: 02/24/1994
• Issued: 05/21/1996
• Est. Priority Date: 02/26/1993
• Status: Expired due to Fees

• Current Assignee: Magneti Marelli France (Stellantis NV)
• Original Assignee: Magneti Marelli France (Stellantis NV)
• Inventors: Poletto, Vanni, Poma, Alberto, Chapotot, Michel, Marteau, Bernard, Philippon, Xavier
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/201,228
• Time in Patent Office: 817 Days
• Field of Search: 341/153, 341/154, 341/155, 341/163, 341/164, 340/450.2
• US Class Current: 341/155
• CPC Class Codes: G01D 1/02 giving mean values, e.g. root means square values measuring root mean square values of currents or voltages G01R19/02
• CPC Class Codes: G01D 3/02 with provision for altering or correcting the law of variation

Abstract

The present invention relates to a circuit for processing the output signal from a resistive analog sensor, comprising firstly a digital filter, and secondly a module forming a digital-to-impedance converter, which filter and module are interposed in series between the output of the sensor and the input of an associated load, the digital-to-impedance converter presenting an output impedance that is variable as a function of the output signal from the digital filter, which is equivalent to the output resistance of the sensor.

Claims

1. A circuit for processing the output signal from a resistive analog sensor, comprising firstly digital filter means, and secondly a module forming a digital-to-impedance converter, which means and module are interposed in series between the output of the sensor and the input of an associated load, said digital-to-impedance converter presenting an output impedance that is variable as a function of the output signal from the digital filter means, which output impedance is equivalent to the output resistance of the sensor.

2. A circuit according to claim 1, wherein the digital-to-impendance converter comprises means for measuring the voltage at the terminals of the load and an output stage of the controlled current source type for delivering a current that is proportional to the ratio between the voltage measured at the terminals of the load and the output resistance of the sensor.

3. A circuit according to claim 2, wherein the control means of the current source comprise a variable gain amplifier connected to one input of a comparator whose other input is connected to the input of the load and whose output is connected to the current source.

4. A circuit according to claim 3, wherein the variable gain amplifier comprises an attenuator constituted by a resistor array driven by the output of the digital filter means.

5. A circuit according to claim 4, wherein the variable gain amplifier comprises a first amplifier stage, the attenuator constituted by the resistor array, and a second amplifier stage.

6. A circuit according to claim 4, wherein the resistor array comprises a divider bridge having a plurality of resistors of resistance R connected in series via a resistor of resistance 2R between ground and the output of the array, each common point between two adjacent resistors of said divider bridge, and the output point thereof also being connected via respective resistors of resistance 2R to respective switches, each switch being respectively controlled by one of the outputs of the digital filter means in such a manner that each switch connects the corresponding resistor either to ground, or to a reference voltage.

7. A circuit according to claim 4, wherein the resistor array comprises a divider bridge comprising a plurality of resistors of resistance R connected in series via a resistor of resistance 2R between ground and a reference voltage, each point common to two adjacent resistors in said divider bridge and its end point receiving the reference voltage also being connected via a respective resistor of resistance 2R to a respective switch, the switches being driven by respective associated outputs of the digital filter means in such a manner that each switch connects the corresponding resistor either to ground or to the input of an amplifier stage.

8. A circuit according to claim 2, wherein the means for measuring the voltage at the terminals of the load include a resistive divider bridge.

9. A circuit according to claim 2, wherein the current source type output stage comprises a transistor connected in series with the sensor.

10. A circuit according to claim 2, wherein the current source type output stage comprises two parallel-connected branches each including a transistor.

11. A circuit according to claim 10, wherein a first branch comprises a resistor connected in series with a transistor, and the second branch comprises a resistor connected in series with a transistor and with the sensor.

12. A circuit according to claim 10, wherein one of the transistors is driven by an operational amplifier that receives on respective inputs both the voltage signal as measured at the terminals of the load and the output signal from the filter.

13. A circuit according to claim 12, wherein one of the transistors is driven by an operational amplifier that receives on respective inputs the potentials present at respective intermediate points of the two branches.

14. A circuit according to claim 10, wherein one of the transistors is driven by an operational amplifier that receives on respective inputs both the voltage signal as measured at the terminals of the load and the output signal from the filter, wherein the digital filter means comprise a comparator stage having a first input receiving the output signal from the sensor, an up/down counter having an input that receives a clock signal at constant frequency, and having an up/down control input that receives the output from the comparator stage, a digital filter whose input is connected to the output of the up/down counter, and an analog-to-digital converter connected between the output of the digital filter and a second input of the comparator, and wherein a sample-and-hold circuit is interposed between the output of the analog-to-digital converter and one of the inputs of the operational amplifier.

15. A circuit according to claim 1, wherein the digital-to-impedance converter is constituted by a resistor array and by an impedance converter.

16. A circuit according to claim 15, wherein the impedance converter comprises a unit comprising in series a current generator and a resistor connected to the input terminal of the load, and means for controlling the current generator.

17. A circuit according to claim 16, wherein the means for controlling the current generator comprise a resistor array driven by the digital filter means.

18. A circuit according to claim 16, wherein the means for controlling the current generator are responsive to the voltage present at the input terminals of the load.

19. A circuit according to claim 15, wherein the impedance converter comprises a shunt resistor connected in series with the output of the resistor array, a first voltage-copying stage suitable for copying the voltage that is present at the input of the load onto the output terminals of the resistor array, a current generator connected in series with a resistor forming a unit connected to the input terminals of the load, and a second voltage-copying stage suitable for copying the voltage present at the terminals of the shunt resistor onto the resistor that is connected in series with the current source.

20. A circuit according to claim 19, wherein the resistor connected in series with the current generator is of smaller resistance than the shunt resistor, typically being equal to one-thousandth of the resistance of the shunt.

21. A circuit according to claim 19, wherein the resistor array comprises a set of switches connected in series, driven by respective different bits of the output signal of the digital filter means and connected in parallel with respective associated resistors.

22. A circuit according to claim 21, wherein the resistors are of resistances that increase progressively in application of the relationship 2ⁿ R in which n is a positive integer.

23. A circuit according to claim 15, wherein the resistor array is driven by the more significant output bits from the digital filter means.

24. A circuit according to claim 1, wherein the digital-to-impedance converter comprises a digital-to-analog converter and an analog to impedance converter.

25. A circuit according to claim 1, wherein the control means for the current source comprise digital calculation means.

26. A circuit according to claim 25, wherein the digital calculation means have one input connected to the input of the load via an analog-to-digital converter and their output connected to the control input of the current source via a digital-to-analog converter.

27. A circuit according to claim 1, wherein the control means of the current source comprise analog calculation means.

28. A circuit according to claim 27, wherein the control means receives analog data representative of the output resistance of a resistor array under the control of the digital filter means.

29. A circuit according to claim 1, wherein the digital filter means comprise a comparator stage having a first input receiving the output signal from the sensor, an up/down counter having an input that receives a clock signal at a constant frequency, and having an up/down control input that receives the output from the comparator stage, and a resistor array connected between the output of the up/down counter and a second input of the comparator stage.

30. A circuit according to claim 29, wherein the resistor array comprises a divider bridge having a plurality of resistors of resistance R connected in series via a resistor of resistance 2R between ground and the output of the array, each common point between two adjacent resistors of said divider bridge, and the output point thereof also being connected via respective resistors of resistance 2R to respective switches, each switch being respectively controlled by one of the outputs of the digital filter means in such a manner that each switch connects the corresponding resistor either to ground, or to a reference voltage.

31. A circuit according to claim 29, wherein the resistor array comprises a divider bridge comprising a plurality of resistors of resistance R connected in series via a resistor of resistance 2R between ground and a reference voltage, each point common to two adjacent resistors in said divider bridge and its end point receiving the reference voltage also being connected via a respective resistor of resistance 2R to a respective switch, the switches being driven by respective associated outputs of the digital filter means in such a manner that each switch connects the corresponding resistor either to ground or to the input of an amplifier stage.

32. A circuit according to claim 29, including means suitable for modifying the frequency of the clock signal when switched on.

33. A circuit according to claim 32, wherein the means generating the clock signal comprise an oscillator and a divider connected in cascade, and wherein the means for modifying the frequency of the clock signal comprise means suitable for inhibiting the divider at switch on.

34. A circuit according to claim 33, wherein the inhibition means are connected to the output of the comparator stage to interrupt inhibition of the divider after a predetermined number of zero crossings have been detected in the output of the comparator stage.

35. A circuit according to claim 1, wherein the digital filter means comprise a series connection of an analog-to-digital converter and a digital filter.

36. A circuit according to claim 1, wherein the digital filter means comprise a comparator stage having a first input receiving the output signal from the sensor, an up/down counter having an input that receives a clock signal at constant frequency, and having an up/down control input that receives the output from the comparator stage, a digital filter whose input is connected to the output of the up/down counter, and an analog-to-digital converter connected between the output of the digital filter and a second input of the comparator.

37. A circuit according to claim 1, wherein the filter means comprise control means including:

detection means suitable for detecting crossovers between the input signal and a filtered value of said input signal;

timing means restarted on each crossover detected by the detection means; and

inhibit means for inhibiting the filter if no crossover is detected by the detection means before the timing means have timed out, and for enabling the filter on the first crossover that is detected by the detection means after the filter has been inhibited.

38. A circuit according to claim 37, wherein the digital filter means comprises a first order filter.

39. A circuit according to claim 37, wherein the digital filter means is of the form:

space="preserve" listing-type="equation">filter.sub.n =filter.sub.n-1 +[Mniv/P]Mniv×

(NIV.sub.n -filter.sub.n-1)/P

where;

filter_n designates the value of the filter signal at instant n;

filter_n-1 designates the value of the filter signal at instant n-1;

Mniv designates a multiplicative factor;

NIV_n designates the input value measured at instant n;

P designates a time constant; and

n is a positive integer.

40. A circuit according to claim 37, wherein the time out of the timing means is of the order of 1 second to 2 seconds.

41. A circuit according to claim 37, wherein the inhibit means comprise means suitable for changing the time constant of the filter.

42. A circuit according to claim 41, wherein the means suitable for modifying the time constant of the filter are adapted to modify a multiplicative factor of the filter function so as to increase the filter time constant during the inhibit period.

43. A circuit according to claim 37, wherein the filter means comprise means suitable for preventing the inhibit means from operating when the circuit is switched on until the detection means have detected a predetermined number of crossovers between the input signal and the filtered value of said input signal.

44. A circuit according to claim 37, including non-linear means suitable for compensating the non-linearity of the combination of sensor and the load.

45. A circuit according to claim 44, including an analog-to-digital converter that is non-linear.

46. A circuit according to claim 44, including means suitable for modifying the time constant of the filter as a function of the non-linear response of the combination comprising the sensor and the load.

47. A circuit according to claim 46, wherein the means for modifying the time constant of the filter act on a multiplicative factor in the filter function.

48. A circuit according to claim 47, wherein the multiplicative factor Mniv in the filter function is of the form:

space="preserve" listing-type="equation">[Mniv=16(2-NIV.sub.max ]16(2NIV.sub.max -NIV.sub.n /NIV.sub.max)

wherein NIV_max represents the maximum amplitude of the signal available at the input of the filter.

49. A circuit according to claim 1, wherein the digital filter means and the module constituting the digital-to-impedance converter are implemented in the form of a single integrated circuit.

50. A circuit according to claim 1, wherein said circuit is located in the sensor.

51. A circuit according to claim 1, wherein said circuit is located in the load.

52. A circuit according to claim 1, wherein the sensor is a resistive sensor, in particular for measuring the level of a liquid.

53. A circuit according to claim 1, wherein the sensor is a potentiometer type sensor, fed with a regulated voltage from which output data is taken by means of the wiper of the potentiometer.

54. A circuit according to claim 1, wherein the sensor is of the rheostat type, fed by a current source, and from which output data is taken from the terminals of the variable resistance constituted in this way.

55. A circuit according to claim 1, wherein the current flowing through the sensor is less than the current flowing through the load.

56. A circuit according to claim 1, wherein the sensor is fed with alternating current and a rectifier circuit is provided between the output from the sensor and the input to the digital filter means.

57. A circuit according to claim 1, wherein the load is constituted by a meter, preferably by a ratio meter.

58. A circuit according to claim 1, further comprising:

a comparator having a first input on which it receives the voltage at the terminals of the sensor;

an up/down counter having an up/down control input connected to the output of the comparator;

a digital filter whose input is connected to the output of the up/down counter;

a multiplexer whose inputs are connected respectively to the output of the up/down counter and to the output of the digital filter;

a digital-to-analog converter whose input is connected to the output of the multiplexer and whose output is connected to the second input of the up/down counter;

a sample-and-hold circuit whose input is connected to the output of the digital-to-analog converter; and

a control circuit that controls a current source at the output of the circuit as a whole on the basis of the voltage measured at the terminals of the load and of the signal from the sample-and-hold circuit.

59. A circuit according to claim 1, further comprising a current source that feeds the sensor, which current source is controlled to deliver a current proportional to the output current supplied to the load.

60. A circuit according to claim 1, further comprising:

an analog-to-digital converter whose input is connected to the output of the sensor;

a digital filter whose input is connected to the output of the analog-to-digital converter;

a digital-to-analog converter whose input is connected to the output of the digital filter;

an attenuator whose input is connected to the load; and

an output current source which is driven by the difference between the signal from the digital-to-analog converter and the signal from the attenuator.