Apparatus and method for converting an HDTV signal to a non-HDTV signal

• US 5,519,446 A
• Filed: 11/14/1994
• Issued: 05/21/1996
• Est. Priority Date: 11/13/1993
• Status: Expired

• Current Assignee: Goldstar Co., Ltd. (LG Corporation)
• Original Assignee: Goldstar Jewellery LLC
• Inventors: Lee, Dong H.
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US08/339,721
• Time in Patent Office: 554 Days
• Field of Search: 348/556, 348/553, 348/402, 348/555, 348/443, 348/441, 348/449
• US Class Current: 348/556
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/40 using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
• CPC Class Codes: H04N 19/587 involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0125 one of the standards being a high definition standard
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Abstract

A digital video signal reception apparatus comprising a multiplexer selection controller for outputting a plurality of control signals according to a format of a compressed input digital video signal, a decoder for decoding the compressed input digital video signal, a frame rate conversion circuit for convening a frame rate of the decoded digital video signal from the decoder into a desired value under the control of the multiplexer selection controller, a multiplexer for selecting one of the decoded digital video signal from the decoder and an output video signal from the frame rate conversion circuit under the control of the multiplexer selection controller, a decimation circuit for performing a decimation operation to convert the number of horizontal scanning lines of an output video signal from the multiplexer into a desired value, a display mode conversion circuit for performing a display mode conversion operation so that an output video signal from the decimation circuit can be displayed in a desired display mode, and a display processor for displaying an output video signal from the display mode conversion circuit on a screen of a monitor. The received video signal can be displayed on an existing non-high definitions TV receiver in various display modes. Therefore, the user can view an HDTV broadcasting even on the existing non-high definitions TV receiver.

Claims

1. A digital video signal reception apparatus comprising:

multiplexer selection control means for outputting a plurality of control signals according to a format of a compressed input digital video signal;

decoding means for decoding the compressed input digital video signal;

frame rate conversion means for convening a frame rate of the decoded digital video signal from said decoding means into a desired value under the control of said multiplexer selection control means;

first multiplexing means for selecting one of the decoded digital video signal from said decoding means and an output video signal from said frame rate conversion means under the control of said multiplexer selection control means;

decimation means for performing a decimation operation to convert the number of horizontal scanning lines of an output video signal from said first multiplexing means into a desired value;

display mode conversion means for performing a display mode conversion operation so that an output video signal from said decimation means can be displayed in a desired display mode; and

display processing means for displaying an output video signal from said display mode conversion means on a screen of a monitor.

2. A digital video signal reception apparatus as set forth in claim 1, wherein said decoding means includes:

a variable length decoder/demultiplexer circuit for decoding the compressed input digital video signal;

an inverse quantizer for inverse-quantizing discrete cosine transform coefficients from said variable length decoder/demultiplexer circuit;

an inverse discrete cosine transform unit for performing an inverse discrete cosine transform with respect to the inverse-quantized discrete cosine transform coefficients from said inverse quantizer to obtain a displaced frame difference signal indicative of a difference between previous and present frames;

a frame memory for storing a restored video signal of the previous frame;

a motion compensator for compensating for a motion of a video signal of the present frame on the basis of the restored video signal of the previous frame from said frame memory and motion information from said variable length decoder/demultiplexer circuit and outputting the motion-compensated video signal to said frame memory;

an adder for adding the displaced frame difference signal from said inverse discrete cosine transform unit and the motion-compensated video signal from said frame memory to restore the video signal of the present frame and outputting the restored video signal of the present frame to said frame memory; and

a slice buffer for inputting the restored video signal of the present frame from said adder in units of blocks and outputting the inputted video signal in units of lines.

3. A digital video signal reception apparatus as set forth in claim 1, wherein said frame rate conversion means includes:

a first memory for storing the decoded digital video signal from said decoding means to convert the frame rate thereof into 30 Hz if it is 60 Hz;

second and third memories for storing the decoded digital video signal from said decoding means to convert the frame rate thereof into 30 Hz if it is 24 Hz;

a memory controller for controlling said first to third memories;

a first multiplexer for selecting alternately output video signals from said second and third memories; and

a second multiplexer for selecting one of output video signals from said first memory and said first multiplexer under the control of said multiplexer selection control means.

4. A digital video signal reception apparatus as set forth in claim 1, wherein said decimation means includes:

2;

1 decimation means for performing a 2;

1 decimation operation with respect to the output video signal from said first multiplexing means;

3;

2 decimation means for performing a 3;

2 decimation operation with respect to the output video signal from said first multiplexing means; and

second multiplexing means for selecting one of the output video signal from said first multiplexing means, an output video signal from said 2;

1 decimation means and an output video signal from said 3;

2 decimation means under the control of said multiplexer selection control means.

5. A digital video signal reception apparatus as set forth in claim 1, wherein said display mode conversion means includes:

a plurality of NTSC conversion means, each of said plurality of NTSC conversion means for converting a display mode of the output video signal from said decimation means into the desired display mode; and

second multiplexing means for selecting one of the output video signal from said decimation means and an output video signals from said plurality of NTSC conversion means according to a user'"'"'s selection.

6. A digital video signal reception apparatus as set forth in claim 5, wherein said desired display mode includes:

a first display mode of displaying the output video signal from said decimation means directly at an aspect ratio of 16;

9;

a second display mode of removing both side screen portions of the output video signal from said decimation means and displaying the resultant video signal at an aspect ratio of 4;

3;

a third display mode of decimating vertically and horizontally the output video signal from said decimation means to display it at the aspect ratio of 4;

3 with no loss of the contents and processing upper and lower screen portions of the resultant video signal in black; and

a fourth display mode of decimating horizontally the output video signal from said decimation means and displaying the resultant video signal at the aspect ratio of 4;

3.

7. A digital video signal reception apparatus as set forth in claim 1, wherein said multiplexer selection control means is adapted to control said frame rate conversion means according to whether a frame rate of the compressed input digital video signal is 24 Hz or 60 Hz, to control said first multiplexing means according to whether the frame rate of the compressed input digital video signal is 30 Hz and to control said decimation means according to the number of horizontal scanning lines of the compressed input digital video signal.

8. A digital video signal reception apparatus as set forth in claim 4, wherein said 2:

1 decimation means includes;

2;

1 vertical decimation means for performing a 2;

1 vertical decimation operation with respect to the output video signal from said first multiplexing means; and

2;

1 horizontal decimation means for performing a 2;

1 horizontal decimation operation with respect to an output video signal from said 2;

1 vertical decimation means.

9. A digital video signal reception apparatus as set forth in claim 4, wherein said 3:

2 decimation means includes;

3;

2 vertical decimation means for performing a 3;

2 vertical decimation operation with respect to the output video signal from said first multiplexing means; and

3;

2 horizontal decimation means for performing a 3;

2 horizontal decimation operation with respect to an output video signal from said 3;

2 vertical decimation means.

10. A digital video signal reception apparatus as set forth in claim 5, wherein each of said plurality of NTSC conversion means includes:

a memory for storing the output video signal from said decimation means in units of lines, each line including a plurality of pixels; and

a memory controller for controlling said memory to read only desired pixels therefrom.

11. A digital video signal reception apparatus as set forth in claim 5, wherein each of said plurality of NTSC conversion means includes:

horizontal decimation means for performing a horizontal decimation operation with respect to the output video signal from said decimation means at a desired ratio;

a frame memory for storing an output video signal from said horizontal decimation means; and

a memory controller for controlling said frame memory to decimate vertically the output video signal from said horizontal decimation means and set components of the resultant video signal, to be displayed in black, to "0".

12. A digital video signal reception apparatus as set forth in claim 5, wherein each of said plurality of NTSC conversion means includes:

a demultiplexer for demultiplexing the output video signal from said decimation means and providing a first desired number of output signals; and

a multiplexer for multiplexing a second desired number of the output signals from said demultiplexer;

said first and second desired numbers being determined to perform a horizontal decimation operation with respect to the output video signal from said decimation means at a desired ratio.

13. A digital video signal reception apparatus as set forth in claim 8, wherein said 2:

1 vertical decimation means includes;

a plurality of line delays connected in series to delay the output video signal from said first multiplexing means;

a filter for filtering the output video signal from said first multiplexing means and output video signals from said plurality of line delays;

a memory for storing an output video signal from said filter; and

a memory controller for controlling said memory to perform a write operation with respect to the output video signal from said filter in such a manner that one of two successive lines thereof is skipped, in groups of two lines.

14. A digital video signal reception apparatus as set forth in claim 8, wherein said 2:

1 horizontal decimation means includes;

a plurality of latches connected in series to delay the output video signal from said 2;

1 vertical decimation means;

a filter for filtering the output video signal from said 2;

1 vertical decimation means and output video signals from said plurality of latches; and

a latch for performing a latching operation with respect to an output video signal from said filter in such a manner that one of two successive pixels thereof is skipped, in groups of two pixels.

15. A digital video signal reception apparatus as set forth in claim 9, wherein said 3:

2 vertical decimation means includes;

a line delay for delaying the output video signal from said first multiplexing means in units of lines;

an adder and a divider for taking the average of the output video signal from said first multiplexing means and an output video signal from said line delay;

a multiplexer for selecting alternately the output video signal from said first multiplexing means and output video signal from said divider;

a memory for storing an output video signal from said multiplexer; and

a memory controller for controlling said memory to read alternately the output video signal from said first multiplexing means and the output video signal from said divider.

16. A digital video signal reception apparatus as set forth in claim 9, wherein said 3:

2 horizontal decimation means includes;

a latch for delaying the output video signal from said 3;

2 vertical decimation means in units of pixels;

an adder and a divider for taking the average of the output video signal from said 3;

2 vertical decimation means and an output video signal from said latch;

a multiplexer for selecting alternately the output video signal from said 3;

2 vertical decimation means and an output video signal from said divider;

a 1;

3 demultiplexer for 1;

3-demultiplexing an output video signal from said multiplexer; and

a 2;

1 multiplexer for 2;

1-multiplexing selected two of output signals from said 1;

3 demultiplexer.

17. A digital video signal reception apparatus as set forth in claim 11, wherein said horizontal decimation means includes:

a demultiplexer for demultiplexing the output video signal from said decimation means and providing a first desired number of output signals; and

a multiplexer for multiplexing a second desired number of the output signals from said demultiplexer;

said first and second desired numbers being determined to perform the horizontal decimation operation with respect to the output video signal from said decimation means at the desired ratio.

18. A digital video signal reception apparatus as set forth in claim 1, wherein said decoding means includes:

a variable length decoder/demultiplexer circuit for decoding the compressed input digital video signal;

a macro block memory for storing discrete cosine transform coefficients from said variable length decoder/demultiplexer circuit in units of macro blocks and outputting only ones of the stored discrete cosine transform coefficients corresponding to low-frequency components in units of blocks of a desired size;

an inverse quantizer for inverse-quantizing the discrete cosine transform coefficients from said macro block memory according to macro block type and quantization level information from said variable length decoder/demultiplexer circuit;

an inverse discrete cosine transform unit for performing an inverse discrete cosine transform with respect to the inverse-quantized discrete cosine transform coefficients from said inverse quantizer to obtain a displaced frame difference signal indicative of a difference between previous and present frames;

a frame memory for storing a restored video signal of the previous frame;

a divider for scaling motion information from said variable length decoder/demultiplexer circuit at a desired ratio;

a motion compensator for compensating for a motion of a video signal of the present frame on the basis of the restored video signal of the previous frame from said frame memory and the motion information scaled by said divider and outputting the motion-compensated video signal to said frame memory;

an adder for adding the displaced frame difference signal from said inverse discrete cosine transform unit and the motion-compensated video signal from said frame memory to restore the video signal of the present frame and outputting the restored video signal of the present frame to said frame memory; and

a slice buffer for inputting the restored video signal of the present frame from said adder in the unit of block and outputting the inputted video signal in the unit of line.

19. A digital video signal reception apparatus as set forth in claim 18, wherein said macro block memory is adapted to store the discrete cosine transform coefficients from said variable length decoder/demultiplexer circuit in units of macro blocks and output only ones of the stored discrete cosine transform coefficients corresponding to the low-frequency components in units of 4×

4 blocks.

20. A digital video signal reception apparatus as set forth in claim 18, wherein said inverse quantizer is adapted to inverse-quantize the discrete cosine transform coefficients from said macro block memory in units of 4×

4 blocks.

21. A digital video signal reception apparatus as set forth in claim 18, wherein said inverse discrete cosine transform unit is adapted to perform the inverse discrete cosine transform with respect to the inverse-quantized discrete cosine transform coefficients from said inverse quantizer in units of 4×

4 blocks.

22. A digital video signal reception apparatus as set forth in claim 18, wherein a counter is included instead of said macro block memory in said decoding means to input the discrete cosine transform coefficients from said variable length decoder/demultiplexer circuit and output only ones of the inputted discrete cosine transform coefficients corresponding to the low-frequency components to said inverse quantizer.

23. A digital video signal reception apparatus as set forth in claim 18, wherein said divider is adapted to scale the motion from said variable length decoder/demultiplexer circuit by 1/2.