Protection circuit for electric cells from overcharge and overdischarge using a plurality of detection units of a single chip type

• US 5,519,563 A
• Filed: 07/06/1995
• Issued: 05/21/1996
• Est. Priority Date: 07/06/1994
• Status: Expired due to Fees

• Current Assignee: Mitsumi Electric Co., Ltd. (MinebeaMitsumi Inc.)
• Original Assignee: Mitsumi Electric Co., Ltd. (MinebeaMitsumi Inc.)
• Inventors: Makime, Kyozo, Higashijima, Yasuhisa
• Primary Examiner(s): DeBoer, Todd
• Application Number:
  US08/498,906
• Time in Patent Office: 320 Days
• Field of Search: 361/16, 361/15, 361/86, 320/14, 320/18, 320/39, 320/40, 320/43, 324/434
• US Class Current: 361/16
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits

Abstract

In a protection circuit for protecting a plurality of chargeable electric cells by detecting overdischarge and overcharge by detection circuits for respective electric cells to control a protection switch upon detection, the detection circuit is a single chip device comprising an overcharge detection circuit and an overdischarge detection circuit to produce first and second detection signals, respectively, first and second terminals to be connected to an electric cell, third and fourth terminals for receiving first and second input signals, respectively, and fifth and sixth terminals for delivering first and second output signals, respectively. The first input signal and the first detection signal are processed by an OR gate to produce a first processed signal which is delivered to the fifth terminal. The second input signal and the second detection signal are processed by AND gate to produce a second processed signal which is delivered to the sixth terminal. In protection of a plurality of electric cells, the detection units are connected to electric cells, respectively, and connected in a cascaded form so that the first and second output signals from one stage of detection units are transmitted as first and second input signals to the next succeeding stage of the detection units in the cascaded form Accordingly, the overcharge and overdischarge detected in any one of stages are transmitted to the protection switch through the succeeding stages.

Claims

1. A protection circuit for use in protection of first to n-th chargeable electric cells from over-charge and over-discharge, n being an integer of 2 or more, said first to n-th electric cells being connected in series with each other in this order to form a series of electric cell row, said series of electric cell row being connected across a selected one of a load and a charging power supply, which comprises:

a first connection member and a second connection member to be connected to opposite terminals of said selected one of the load and the charging power supply, said first connection member being connected to one end electrode of said series of electric cell row;

protection switching means through which said second connection member is connected to the opposite end electrode of said series of electric cell row, said protection switching means connecting said electric cell row to said selected one of said load and said charging power supply when said protection switch is in an ON condition, said protection switching means disconnecting said electric cell row from said selected one of said load and said charging power supply to protect said electric cells when said protection switch is in an OFF condition; and

first to n-th detection circuit units connected across corresponding ones of said first to n-th electric cells for detecting overdischarge and overcharge of the corresponding electric cells, respectively;

each of said first to n-th detection circuit units being a single chip device which comprises;

a first terminal and a second terminal to be connected to opposite electrodes of the corresponding one of said first to n-th electric cells, respectively, for receiving an output voltage across the opposite electrodes of said corresponding electric cell;

a third terminal and a fourth terminal for receiving a first and a second input signals, respectively;

a fifth and a sixth terminals for delivering a first and a second output signals, respectively;

a seventh and an eighth terminals for delivering a third and a fourth output signals corresponding to said first and said second output signals, respectively;

an overcharge detection circuit connected between said first and said second terminals for detecting whether or not said output voltage is higher than a first reference voltage having a first reference voltage level to produce a first detection signal, said first detection signal being representative of an overcharge detection signal when said output voltage is higher than said first reference voltage;

an overdischarge detection circuit connected between said first and said second terminals for detecting whether or not said output voltage is lower than a second reference voltage having a second reference voltage level which is lower than said first reference voltage level to produce a second detection signal, said second detection signal being representative of an overdischarge detection signal when said output voltage is lower than said second reference voltage;

a first processing circuit coupled to said third terminals, said overcharge detection circuit, said fifth terminal and said seventh terminal for processing said first input signal and said first detection signal to produce a first processed signal, said first processed signal being provided to said fifth terminal and said seventh terminal as said first output signal and said third output signal, said first output signal and said third output signal being representative of said overcharge detection signal when any one of said first input signal and said first detection signal is representative of said overcharge detection signal; and

a second processing circuit coupled to said fourth terminal, said overdischarge detection circuit, said sixth terminal and said eighth terminal for processing said second input signal and said second detection signal to produce a second processed signal, said second processed signal being provided to said sixth terminal and said eighth terminal as said second output signal and said fourth output signal, said second output signal and said fourth output signal being representative of said overdischarge detection signal when any one of said second input signal and said second detection signal is representative of said overdischarge detection signal;

said fifth and said sixth terminals of a m-th one of said first to n-th detection circuit units, m being an integer equal to 1 or more but smaller than n, being connected to said said third and said fourth terminals of a (m+1)-th one of said first to n-th detection circuit units, respectively; and

said seventh and said eighth terminals of said n-th detection circuit unit being coupled to said protection switching means, said protection switching means being turned into said OFF condition when said third output signal said seventh terminal is representative of said overcharge detection signal or when said fourth output signal said eighth terminal is representative of said overdischarge detection signal.

2. A protection circuit as claimed in claim 1, wherein said third and said fourth terminals of said first detection circuit unit are commonly connected to said first terminal of said first detection circuit unit.

3. A protection circuit as claimed in claim 1, wherein said fifth and said Sixth terminals of said n-th detection circuit unit are commonly connected to said second terminal of said n-th detection circuit unit.

4. A protection circuit as claimed in claim 1, wherein said protection switching means comprises first and second switching elements connected in series with each other, said first switching element being controlled by said third output signal from said n-th detection circuit unit, said second switching element being controlled by said fourth output signal from said n-th detection circuit unit.

5. A protection circuit as claimed in claim 1, wherein said second detection signal is a low level signal when said overdischarge is detected, but is a high level signal when overdischarge is not detected.

6. An electric cell unit comprising:

first to n-th, n being an integer of 2 or more, chargeable electric cells being connected in series with one another to form a series of electric cell row, said series of electric cell row being connected to across a selected one of a load and a charging power supply; and

a protection circuit for protecting said first to n-th electric cells from overdischarge and overcharge, said protection circuit comprising;

a first connection member and a second connection member to be connected to opposite terminals of said selected one of the load and the charging power supply, said first connection member being connected to one end electrode of said series of electric cell row;

protection switching means through which said second connection member is connected to the opposite end electrode of said series of electric cell row, said protection switching means connecting said electric cell row to said selected one of said load and said charging power supply when said protection switch is in an ON condition, said protection switching means disconnecting said electric cell row from said selected one of said load and said charging power supply to protect said electric cells when said protection switch is in an OFF condition; and

first to n-th detection circuit units connected across corresponding ones of said first to n-th electric cells for detecting overdischarge and overcharge of the corresponding electric cells, respectively;

each of said first to n-th detection circuit units being a single chip device which comprises;

a first terminal and a second terminal to be connected to opposite electrodes of the corresponding one of said first to n-th electric cells, respectively, for receiving an output voltage across the opposite electrodes of said corresponding electric cell;

a third terminal and a fourth terminal for receiving a first and a second input signals, respectively;

a fifth and a sixth terminals for delivering a first and a second output signals, respectively;

a seventh and an eighth terminals for delivering a third and a fourth output signals corresponding to said first and said second output signals, respectively;

an overcharge detection circuit connected between said first and said second terminals for detecting whether or not said output voltage is higher than a first reference voltage having a first reference voltage level to produce a first detection signal, said first detection signal being representative of an overcharge detection signal when said output voltage is higher than said first reference voltages;

an overdischarge detection circuit connected between said first and said second terminals for detecting whether or not said output voltage is lower than a second reference voltage having a second reference voltage level which is lower than said first reference voltage level to produce a second detection signal, said second detection signal being representative of an overdischarge detection signal when said output voltage is lower than said second reference voltage;

a first processing circuit coupled to said third terminals, said overcharge detection circuit, said fifth terminal and said seventh terminal for processing said first input signal and said first detection signal to produce a first processed signal, said first processed signal being provided to said fifth terminal and said seventh terminal as said first output signal and said third output signal, said first output signal and said third output signal being representative of said overcharge detection signal when any one of said first input signal and said first detection signal is representative of said overcharge detection signal; and

a second processing circuit coupled to said fourth terminal, said overdischarge detection circuit, said sixth terminal and said eighth terminal for processing said second input signal and said second detection signal to produce a second processed signal, said second processed signal being provided to said sixth terminal and said eighth terminal as said second output signal and said fourth output signal, said second output signal and said fourth output signal being representative of said overdischarge detection signal when any one of said second input signal and said second detection signal is representative of said overdischarge detection signals;

said fifth and said sixth terminals of a m-th one of said first to n-th detection circuit units, m being an integer equal to 1 or more but smaller than n, being connected to said said third and said fourth terminals of a (m+1)-th one of said first to n-th detection circuit units respectively; and

said seventh and said eighth terminals of said n-th detection circuit unit being coupled to said protection switching means said protection switching means being turned into said OFF condition when said third output signal said seventh terminal is representative of said overcharge detection signal or when said fourth output signal said eighth terminal is representative of said overdischarge detection signal.

7. A detection circuit unit of a single chip type for detecting overdischarge and overcharge of an electric cell for use in protection of a plurality of electric cells connected in series with each other from overdischarge and overcharge, which comprises:

a first terminal and a second terminal to be connected to opposite electrodes of the electric cells, respectively, for receiving an output voltage across the opposite electrodes of said electric cell;

a third terminal and a fourth terminal for receiving a first and a second input signals, respectively;

a fifth and a sixth terminals for delivering a first and a second output signals, respectively;

a seventh and an eighth terminals for delivering a third and a fourth output signals corresponding to said first and said second output signals, respectively;

an overcharge detection circuit connected between said first and said second terminals for defecting whether or not said output voltage is higher than a first reference voltage having a first reference voltage level to produce a first detection signal, said first detection signal being representative of an overcharge detection signal when said output voltage Is higher than said first reference voltage;

an overdischarge detection circuit connected between said first and said second terminals for detecting whether or not said output voltage is lower than a second reference voltage having a second reference voltage level which is lower than said first reference voltage level to produce a second detection signal, said second detection signal being representative of an overdischarge detection signal when said output voltage is lower than said second reference voltage;

a first processing circuit coupled to said third terminals, said overcharge detection circuit, said fifth terminal and said seventh terminal for processing said first input signal and said first detection signal to produce a first processed signal, said first processed signal being provided to said fifth terminal and said seventh terminal as said first output signal and said third output signal said first output signal and said third output signal being representative of said overcharge detection signal when any one of said first input signal and said first detection signal is representative of said overcharge detection signal; and

a second processing circuit coupled to said fourth terminal, said overdischarge detection circuit, said sixth terminal and said eighth terminal for processing said second input signal and said second detection signal to produce a second processed signal, said second processed signal being provided to said sixth terminal and said eighth terminal as said second output signal and said fourth output signal, said second output signal and said fourth output signal being representative of said overdischarge detection signal when any one of said second input signal and said second detection signal is representative of said overdischarge detection signal.