Method of arranging components in semiconductor device

• US 5,519,631 A
• Filed: 06/06/1995
• Issued: 05/21/1996
• Est. Priority Date: 03/15/1989
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Inventors: Okada, Atsuhiko, Nishioka, Seishi
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/469,375
• Time in Patent Office: 350 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method of arranging components in a semiconductor device on a substrate (11), comprising provisionally determining a wiring path (3) so that a predetermined wiring capacitance is not exceeded in a specific network (1) and then performing a wiring process of elements (12) in the specific network within a component placement region (2) determined by the wiring path.

Claims

1. A method of arranging components in a semiconductor device on a substrate having a plurality of rows of component cell areas with wiring channels between the rows and a plurality of I/O cells, comprising the steps of:

(a) determining a number of components in a cell-placement region to be connected to a selected I/O cell,

(b) calculating a wiring capacitance for connection of the selected I/O cell to the components in the cell-placement region to check whether the wiring capacitance exceeds a predetermined limit, prior to an actual connection of the components to the I/O cells;

(c) determining, after said calculating in step (b), that, when the wiring capacitance does not exceed the predetermined limit, the components in the cell-placement region should be connected to the selected I/O cell;

(d) determining, after said determining and calculating in steps (a) and (b), that, when the wiring capacitance exceeds the predetermined limit, said calculating in step (b) should be performed again after the number of the components in the cell-placement region is reduced, and repeating said calculating and determining in steps (b)-(d) until a final size of the cell-placement region is determined;

(e) assigning predetermined cell functions to provide the components in selected component cell areas within the cell-placement region;

(f) assigning wirings between the selected component cell areas and the selected I/O cell, including main conductor lines from the selected I/O cell along the wiring channels and branch conductor lines from the selected component cells to the main conductor lines;

(g) determining initial branch line connections to each of the main conductor lines in sequence from a most weighted main conductor line, having at least as many of the branch conductor lines assigned thereto in step (f) as any other of the main conductor lines, to a least weighted main conductor line, without any of the branch conductor lines initially connected to more than one of the main conductor lines;

(h) determining final branch line connections to the main conductor lines as connections of the branch conductor lines to closest main conductor lines if any of the initial branch line connections cross at least one of the wiring channels and intersects more than one of the main conductor lines;

(i) forming the I/O cells and the components in the selected component cell areas in the cell-placement region on the substrate; and

(j) wiring the components in the cell-placement region to the selected I/O cell by forming the main conductor lines assigned in step (f) and the branch conductor lines to the final branch line connections determined in step (h).

2. A method of arranging components according to claim 1, wherein said substrate has a plurality of rows and a plurality of columns of the component cell areas and a plurality of clock I/O cells surrounding the the component cell areas.

3. A method of arranging components according to claim 2, wherein said calculating in step (b) includes the steps of:

(b1) calculating a number of the rows of the components needed to locate all of the components in the cell-placement region when a predetermined maximum number of the columns of the components is used; and

(b2) calculating a number of the columns of the components needed to locate all of the components in the cell-placement region when the number of the rows calculated in step (b1) is used.

4. A method of arranging components according to claim 3, wherein said calculating in step (b) further includes the step of (b3) calculating the number of the columns of the components needed to locate all of the components in the cell-placement region so that a predetermined wiring capacitance is not exceeded when the number of the rows of the components calculated in step (b1) is used.

5. A method of arranging components according to claim 4, wherein said determining in step (a) includes determining placement of a specific network of the components in the cell-placement region in accordance with selection of an associated clock I/O cell as the selected I/O cell.

6. A method of arranging components according to claim 4,

wherein said assigning in step (f) includes:

(f2) preparing a wiring map showing a predetermined arrangement of the components and the wiring channels between the rows of the components; and

(f2) assigning the main conductor lines in the wiring channels,

wherein said determining in step (g) includes the steps of;

(g1) determining the initial branch line connections from the components in the cell-placement region to the main conductor lines; and

(g2) successively and provisionally selecting the most weighted main conductor line from among the main conductor lines in accordance with a number of points of intersection of the main conductor lines and the initial branch line connections, and

wherein said determining in step (h) includes the step of modifying the main conductor lines provisionally selected in step (g2), taking into account lengths of the branch conductor lines connected thereto.

7. A method of wiring components on a semiconductor substrate, comprising the steps of:

(a) determining a cell placement area for cells on the semiconductor substrate, the cell placement area defined to prevent wiring therein from exceeding a predetermined wiring capacitance;

(b) integrating the components in at least some of the cells on the semiconductor substrate in the cell placement area; and

(c) wiring the components in the cells integrated in step (b) along predetermined wiring paths in the cell placement area, said wiring including the substeps of;

(c1) assigning main conductor lines from an input/output cell along the predetermined wiring paths and branch conductor lines from the components towards the main conductor lines;

(c2) determining branch line connections to each of the main conductor lines in sequence from a most weighted main conductor line, having at least as many intersections with the branch conductor lines assigned in step (c1) as any other of the main conductor lines, to a least weighted main conductor line, with each the branch conductor lines connected to only one of the main conductor lines closest thereto; and

(c3) wiring the components in the cell placement area to the input/output cell by forming the main conductor lines assigned in step (c1) and the branch conductor lines to the branch line connections determined in step (c2).

8. A method of wiring components on a semiconductor substrate, comprising the steps of:

(a) determining a cell placement area for cells on the semiconductor substrate, the cell placement area defined to prevent wiring therein from exceeding a predetermined wiring capacitance, including defining predetermined numbers of rows and columns of the cells with the predetermined wiring paths between the cells;

(b) integrating the components in at least some of the cells on the semiconductor substrate in the cell placement area; and

(c) wiring the components in the cells integrated in step (b) along predetermined wiring paths in the cell placement area, said wiring in step (c) including the substeps of;

(c1) preparing a wiring map of a predetermined arrangement of the cells and the predetermined wiring paths between the rows of the cells;

(c2) assigning main conductor lines in the predetermined wiring paths;

(c3) determining initial branch line connections from the components in the cell placement area to the main conductor lines;

(c4) successively and provisionally selecting a most weighted main conductor line from among the main conductor lines in accordance with a number of points of intersection of the main conductor lines and the initial branch line connections;

(c5) determining final branch line connections to the main conductor lines as branch conductor lines from the components to closest main conductor lines if any of the initial branch line connections cross at least one of the wiring channels and intersects more than one of the main conductor lines; and

(c6) modifying the main conductor lines provisionally selected in step (c4), taking into account lengths of the branch conductor lines connected thereto.

9. A method of arranging components in a semiconductor device on a substrate having a plurality of components and a plurality of I/O cells, comprising the steps of:

(a) calculating a wiring capacitance between one of the I/O cells and the components to check whether the wiring capacitance exceeds a predetermined limit prior to an actual connection of the components to the one of the I/O cells;

(b) determining, after said calculating in step (a), that the components are defined within a cell-placement area on the substrate, when the wiring capacitance does not exceed the predetermined limit;

(c) determining, after said calculating in step (a), that the components are defined outside of the cell placement area when the wiring capacitance exceeds the limit;

(d) assigning predetermined cell functions to the components within the cell-placement area determined in step (b) and assigning predetermined wirings between cells of the components, and between the cells and the one of the I/O cells, in accordance with the predetermined cell functions;

(e) forming the one of the I/O cell and the cells determined in steps (a) and (b), in the cell-placement area on the substrate; and

(f) wiring the cells to associated I/O cells, in the cell-placement area on the substrate.